VPEXTRW instruction (AVX, AVX10.1)

VPEXTRW copies one word of an XMM register to the low 16 bits of a general-purpose register, clearing all the bits above, or stores it to two bytes of memory: the VEX and EVEX form of PEXTRW, whose page covers the immediate and the uses of the baseline. Both opcodes carry over, 0F C5 for a register destination only and 0F 3A 15 for a register or memory, each with a VEX encoding (AVX) and an EVEX one (AVX512BW or AVX10.1), which adds only XMM16 to XMM31. All are 128-bit forms. On Zen 5, vpextrw ecx, xmm0, 0x14, the C5 encoding, took word 4, CFC2h, and cleared the rest of RCX; {store} vpextrw esi, xmm4, 0x31, the 3A 15 encoding with a register, took word 1 and left RSI at 9D90h; and {store} vpextrw word ptr [mem], xmm7, 0xd5 stored word 5 and left the bytes after it alone.

In compiled code

In our builds at -O2 with -march=x86-64-v3 and -march=x86-64-v4, GCC 14 and Clang 23 read v[3] of a vector of eight unsigned shorts with one VPEXTRW, element 0 included, add CWDE for a signed short, and store *p = v[5] with the memory form. A word of the upper half of a ymm register takes VEXTRACTI128 first.

The memory form also stores vectors piece by piece. For d[i*3] = s[i] + 1 over uint16_t arrays at -v3, both compilers add 1 to 16 words in one ymm register and store them with 16 VPEXTRWs to memory, eight from each half; with SSE4.1 alone, GCC kept this loop scalar, as PEXTRW’s page shows.

AMD’s latency spreadsheet for Zen 5 gives VPEXTRW two macro-ops for either destination, two per cycle, using pipes FP0 to FP3 and FP4 or FP5. Its EVEX rows give a latency of two cycles, while its VEX rows give none.

Forms

Every encoding of VPEXTRW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPEXTRW m16, xmm, imm8` VPEXTRW_MEMw_XMMdq_IMMb	`VEX.128.66.0F3A.WIG 15 /r ib`	AVX
`VPEXTRW r32, xmm, imm8` VPEXTRW_GPR32d_XMMdq_IMMb_15	`VEX.128.66.0F3A.WIG 15 /r ib`	AVX
`VPEXTRW r32, xmm, imm8` VPEXTRW_GPR32d_XMMdq_IMMb_C5	`VEX.128.66.0F.WIG C5 /r ib`	AVX
`VPEXTRW r32, xmm, imm8` VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512	`EVEX.128.66.0F3A.WIG 15 /r ib`	AVX10.1 or AVX512BW
`VPEXTRW m16, xmm, imm8` VPEXTRW_MEMu16_XMMu16_IMM8_AVX512	`EVEX.128.66.0F3A.WIG 15 /r ib`	AVX10.1 or AVX512BW
`VPEXTRW r32, xmm, imm8` VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5	`EVEX.128.66.0F.WIG C5 /r ib`	AVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`m16, xmm, imm8`	`r32, xmm, imm8`
Sandy Bridge	5 / 1p15	3 / 1p015
Haswell, Broadwell	2 / 1p5	2 / 1p05
Skylake, Skylake-SP	2 / 1p5	3 / 1p05
Ice Lake	2 / 0.5p15	3 / 1p015
Alder Lake, Sapphire Rapids	19 / 0.5p15	4 / 1p015
Lunar Lake	2 / 0.5V2 V3	4 / 1.5V0 V1 V2 V3
Piledriver	13 / 2FPU1	12 / 1.5EX0 FPFMA FPU0
Zen, Zen 2	5 / 3FPU1 FPU2	2 / 2FPU1 FPU2
Zen 3, Zen 4	2 / 1FP45 FPSt LSU Store	1 / 1FP45
Jaguar	3 / 1FPU1	3 / 1ALU0 FPA FPU0

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Extract: word imm8 of xmm2 goes to m16.

Example: imm8 = 0x05.

With imm8 = 0x05, m16 receives word 5 of xmm2: a5.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

dest.write(xmm2.w[imm8 & 7])  # zero-extended in a register

Run on AMD Zen 5 (EPYC 9645): 6 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPEXTRW m16, xmm, imm8`
`m16`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read
`VPEXTRW r32, xmm, imm8`
`r32`	explicit	write
`xmm`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPEXTRW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_extract_epi16` `int _mm_extract_epi16(__m128i a, const int imm)`	`VPEXTRW r32, xmm, imm8` VEX.128 -mavxwith AVX enabled
`_mm_extract_pi16` `int _mm_extract_pi16(__m64 a, const int n)`	`VPEXTRW r32, xmm, imm8` VEX.128 -mavxwith AVX enabled
`_mm_store_sbh` `void _mm_store_sbh(void *__dp, __m128bh __a)`	`VPEXTRW m16, xmm, imm8` VEX.128 -mavx10.2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512BW_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512BW_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#