VPGATHERDD

VPGATHERDD loads doublewords from scattered addresses, each a base plus a signed 32-bit index times a scale of 1, 2, 4 or 8: d[i] = t[idx[i]] for int tables in one instruction. It is the integer twin of VGATHERDPS, whose page explains the two kinds of mask (a vector of sign bits in the AVX2 form, a mask register in the EVEX form), why the mask ends up cleared and why compiled code rebuilds it before every gather; the two load the same bits. Index and data are both 32 bits wide, so 8 indices in a ymm register fill 8 elements, and 16 in a zmm register 16.

What Zen 5 recorded#

• The register rules are enforced: with the destination also named as the mask of the AVX2 form, and with the destination also the index of the EVEX form, the instruction raised #UD.
• An AVX2 gather whose mask had no sign bit set loaded nothing and left the destination alone, but still cleared the whole mask register.
• Negative indices reached below the base, the same index twice loaded the same doubleword twice, and with a scale of 1 doublewords came from addresses that were not multiples of 4.

In compiled code#

GCC 14 at -O2 kept d[i] = t[idx[i]] over int arrays scalar for -march=x86-64-v3, x86-64-v4 and znver5. Clang 23 kept it scalar for x86-64-v3 too, but for x86-64-v4 used the EVEX form on ymm registers, each gather after a VPXOR that zeroes its destination and a KXNORB that sets the mask, and for znver5 the same on zmm registers with KXNORW.

AMD’s Zen 5 guide lists VPGATHERDD as microcoded at every width. VPGATHERDQ fetches quadwords with 32-bit indices, VPGATHERQQ takes 64-bit ones, and VPSCATTERDD stores doublewords the same way.

In the optimization guide

What the optimization guide says about VPGATHERDD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Where the layout of the data is known, vector loads and shuffles usually beat a gather.
• Gathers and scatters: Issue gathers early, gather many elements at once, use doubleword indices for 32-bit data and zero the destination first.
• Gathers and scatters: Gathers beat scalar loads on Skylake, while AMD lists them as microcode on Zen 3, Zen 4 and Zen 5.
• Gathers and scatters: GCC 14.2 builds no gathers when tuning for Zen 4 or Skylake, and LLVM none for Zen 3.

Crestmont and Gracemont

• Vectors and AVX2: Gathers are microcoded on these cores and take about 50 cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: A gather is a load micro-op for each element plus a few more: LLVM’s models give an eight-element VPGATHERDD 12 micro-ops and a latency of 30 cycles, and the 16-element one of Sapphire Rapids 19 micro-ops.

Haswell and Broadwell

• Gathers: Haswell is the first core with gathers, and each one runs as many micro-ops; Broadwell runs them much faster.

Ice Lake to Rocket Lake

• Vectors and AVX-512: Agner Fog finds gathers efficient, more so than on older cores.

Skylake to Cooper Lake

• Vectors on all parts: Gathers are faster than on Broadwell and beat a sequence of scalar loads unless they fetch only two elements or the data comes from memory rather than the caches.

Zen and Zen+

• Vectors and floating point: Gathers such as VPGATHERDD and VGATHERDPS are microcoded, 20 cycles with YMM registers in AMD’s spreadsheet, and GCC 14.2 builds none when tuning for znver1: vector loads and shuffles do better where the indices are known.

Zen 2

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, in AMD’s spreadsheet and LLVM’s model, so vector loads and shuffles beat them when the indices are known in advance.

Zen 3

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, and a register loaded in pieces is slower than one full-width load, so vector loads and shuffles beat both when the indices are known in advance.

Zen 4

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance, and a register loaded in pieces is slower than one full-width load.

Zen 5

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance.

Vulnerability mitigations

Mitigations of these processor vulnerabilities use VPGATHERDD:

• CVE-2022-40982: Gather Data Sampling

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = mem.index.number
if x in (ymm1.number, ymm3.number):
    fault(UD)
if ymm1.number == ymm3.number:
    fault(UD)
for i in range(VL // 32):
    if ymm3.sd[i] < 0:
        a = mem.index.sd[i] * mem.scale
        ymm1.d[i] = load(mem.base + a, 32)
ymm3.write(0)
# ymm1 is zeroed from bit VL up

if mem.index.number == zmm1.number:
    fault(UD)
for i in range(VL // 32):
    if k1[i]:
        a = mem.index.sd[i] * mem.scale
        zmm1.d[i] = load(mem.base + a, 32)
k1.write(0)  # all of it
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-12

EVEX forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

gather

EVEX forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPGATHERDD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPBLENDD
• VPBLENDVB
• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB

All 138 AVX2 instructions

More AVX10.1 instructions

• VPERMILPD
• VPERMILPS
• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ

All 686 AVX10.1 instructions