x86-64.net

Instruction

VPGATHERDQ

Loads quadwords from memory at addresses formed with a vector of 32-bit indices, for the elements a mask selects.

Extensions
Forms
5 (2 VEX, 3 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPGATHERDQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPGATHERDQ ymm, vm32x, ymm VPGATHERDQ_YMMu64_MEMq_YMMi64_VL256VEX.256.66.0F38.W1 90 /rAVX2
VPGATHERDQ xmm, vm32x, xmm VPGATHERDQ_XMMu64_MEMq_XMMi64_VL128VEX.128.66.0F38.W1 90 /rAVX2
VPGATHERDQ zmm {k}, vm32y VPGATHERDQ_ZMMu64_MASKmskw_MEMu64_AVX512_VL512EVEX.512.66.0F38.W1 90 /rAVX10.1 or AVX512F
VPGATHERDQ xmm {k}, vm32x VPGATHERDQ_XMMu64_MASKmskw_MEMu64_AVX512_VL128EVEX.128.66.0F38.W1 90 /rAVX10.1 or AVX512F + AVX512VL
VPGATHERDQ ymm {k}, vm32x VPGATHERDQ_YMMu64_MASKmskw_MEMu64_AVX512_VL256EVEX.256.66.0F38.W1 90 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPGATHERDQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_i32gather_epi64 __m128i _mm_i32gather_epi64(long long const *m, __m128i i, const int s)

VPGATHERDQ xmm, vm32x, xmm VEX.128 -mavx2

_mm_mask_i32gather_epi64 __m128i _mm_mask_i32gather_epi64(__m128i a, long long const *m, __m128i i, __m128i mask, const int s)

VPGATHERDQ xmm, vm32x, xmm VEX.128 -mavx2

_mm_mmask_i32gather_epi64 __m128i _mm_mmask_i32gather_epi64(__m128i v1_old, __mmask8 mask, __m128i index, void const *addr, const int scale)

VPGATHERDQ xmm {k}, vm32x EVEX.128 -mavx512vl

_mm256_i32gather_epi64 __m256i _mm256_i32gather_epi64(long long const *m, __m128i i, const int s)

VPGATHERDQ ymm, vm32x, ymm VEX.256 -mavx2

_mm256_mask_i32gather_epi64 __m256i _mm256_mask_i32gather_epi64(__m256i a, long long const *m, __m128i i, __m256i mask, const int s)

VPGATHERDQ ymm, vm32x, ymm VEX.256 -mavx2

_mm256_mmask_i32gather_epi64 __m256i _mm256_mmask_i32gather_epi64(__m256i v1_old, __mmask8 mask, __m128i index, void const *addr, const int scale)

VPGATHERDQ ymm {k}, vm32x EVEX.256 -mavx512vl

_mm512_i32gather_epi64 __m512i _mm512_i32gather_epi64(__m256i index, void const *addr, const int scale)

VPGATHERDQ zmm {k}, vm32y EVEX.512 -mavx512f

_mm512_mask_i32gather_epi64 __m512i _mm512_mask_i32gather_epi64(__m512i v1_old, __mmask8 mask, __m256i index, void const *addr, const int scale)

VPGATHERDQ zmm {k}, vm32y EVEX.512 -mavx512f

_mm512_i32logather_epi64 __m512i _mm512_i32logather_epi64(__m512i vindex, void const *base_addr, const int scale)

VPGATHERDQ zmm {k}, vm32y EVEX.512 -mavx512f

_mm512_mask_i32logather_epi64 __m512i _mm512_mask_i32logather_epi64(__m512i src, __mmask8 mask, __m512i vindex, void const *base_addr, const int scale)

VPGATHERDQ zmm {k}, vm32y EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX2GATHER

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.