VPGATHERQD

VPGATHERQD loads doublewords from scattered addresses, each a base plus a signed 64-bit index times a scale, into a destination half as wide as the index register: 2 indices fill the low 64 bits of an XMM register, 4 fill an XMM register and 8 in a ZMM register fill a YMM one. It is the integer form of VGATHERQPS, whose page covers the half-width destination, and VGATHERDPS’s explains the mask that is cleared as elements load. AVX2 has the VEX form, with a vector mask in which the top bit of each doubleword selects; AVX512F adds the EVEX form with a mask register and the ZMM index.

Recorded on Zen 5#

• VEX, vector mask. vpgatherqd xmm1, dword ptr [base + ymm14*4], xmm8 loaded elements 1 and 2, whose mask doublewords had the top bit set, kept elements 0 and 3 of XMM1, and cleared XMM8, the mask, entirely.
• Half an XMM register. With two indices in XMM3 and neither mask bit set, nothing loaded, the low 64 bits of XMM1 stayed, and the register was cleared above them.
• EVEX, mask register. vpgatherqd ymm17{k1}, dword ptr [base + zmm30*1] filled the six elements K1 selects, several from the same unaligned address 24 bytes below the base, kept elements 0 and 3, and left K1 at 0.

In compiled code#

r[i] = t[ix[i]], with int data and long indices, is VPGATHERQD in Clang 23 at -O2 with -march=x86-64-v4, the EVEX form with four indices from a YMM register and a fresh KXNORW before each, and eight from a ZMM register with -march=znver5. GCC 14 keeps the loop scalar at both, and at -march=x86-64-v3 neither compiler uses the VEX form: Clang loads each element and inserts it with VPINSRD. _mm512_i64gather_epi32 is KXNORB and VPGATHERQD in both.

AMD’s Zen 5 latency spreadsheet lists the EVEX VPGATHERQD as microcoded.

In the optimization guide

What the optimization guide says about VPGATHERQD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Where the layout of the data is known, vector loads and shuffles usually beat a gather.
• Gathers and scatters: Issue gathers early, gather many elements at once, use doubleword indices for 32-bit data and zero the destination first.
• Gathers and scatters: Gathers beat scalar loads on Skylake, while AMD lists them as microcode on Zen 3, Zen 4 and Zen 5.

Crestmont and Gracemont

• Vectors and AVX2: Gathers are microcoded on these cores and take about 50 cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: A gather is a load micro-op for each element plus a few more: LLVM’s models give an eight-element VPGATHERDD 12 micro-ops and a latency of 30 cycles, and the 16-element one of Sapphire Rapids 19 micro-ops.

Haswell and Broadwell

• Gathers: Haswell is the first core with gathers, and each one runs as many micro-ops; Broadwell runs them much faster.

Skylake to Cooper Lake

• Vectors on all parts: Gathers are faster than on Broadwell and beat a sequence of scalar loads unless they fetch only two elements or the data comes from memory rather than the caches.

Zen 2

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, in AMD’s spreadsheet and LLVM’s model, so vector loads and shuffles beat them when the indices are known in advance.

Zen 3

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, and a register loaded in pieces is slower than one full-width load, so vector loads and shuffles beat both when the indices are known in advance.

Zen 4

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance, and a register loaded in pieces is slower than one full-width load.

Zen 5

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = mem.index.number
if x in (xmm1.number, xmm3.number):
    fault(UD)
if xmm1.number == xmm3.number:
    fault(UD)
for i in range(VL // 64):
    if xmm3.sd[i] < 0:
        a = mem.index.sq[i] * mem.scale
        xmm1.d[i] = load(mem.base + a, 32)
for i in range(VL // 64, 4):
    xmm1.d[i] = 0
xmm3.write(0)
# xmm1 is zeroed from bit 128 up

if mem.index.number == ymm1.number:
    fault(UD)
for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        ymm1.d[i] = load(mem.base + a, 32)
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
k1.write(0)  # all of it
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-12

EVEX forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

gather

EVEX forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPGATHERQD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPBLENDW
• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPERMPD
• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB

All 686 AVX10.1 instructions