VPGATHERQQ

VPGATHERQQ loads quadwords from scattered addresses, each a base plus a signed 64-bit index times a scale of 1, 2, 4 or 8. It works like VGATHERDPS, whose page explains the mask that selects the elements and is cleared as they load, the register rules that raise #UD, and why compiled code rebuilds the mask before each gather. What sets VPGATHERQQ apart is that the index and the data have the same width: 4 indices in a ymm register fetch 4 quadwords, and 8 in a zmm register fetch 8, so both registers are full. A 32-bit index fetching quadwords, VPGATHERDQ, needs only half a register of indices; a 64-bit index fetching doublewords, VPGATHERQD, fills only half of its destination.

Pointers as indices#

A 64-bit index can hold a whole address. For d[i] = *p[i], an array of pointers, Clang 23 at -O2 gathers with no base register and a scale of 1, vpgatherqq zmm4 {k1}, qword ptr [1*zmm0], which follows eight pointers at once; with a table, d[i] = t[idx[i]] over int64_t indices becomes [rdx + 8*zmm0]. Clang does this on zmm registers for -march=znver4 and znver5 and on ymm for x86-64-v4, skylake-avx512 and icelake-server, and keeps both loops scalar for x86-64-v3, where the VEX form exists. GCC 14 vectorized neither loop for any of these targets. Each element’s address needs no alignment.

Cost#

AMD’s Zen 5 guide lists VPGATHERQQ as microcoded, like every gather, and advises vector loads and shuffles instead when the indices are known in advance (Section 2.11.2). Intel’s optimization guide lists the access patterns that suit loads and shuffles better, sequential elements, fewer than four of them, small strides and transpositions, and those that suit a gather, such as indices computed in vector registers or loads that depend on a condition per element (Section 15.16.4, Examples 15-43 and 15-44). It also notes that the latency of a 256-bit gather is less than twice that of a 128-bit one, so wider gathers pay off better.

VPSCATTERQQ stores quadwords the same way, and VGATHERQPD loads doubles with 64-bit indices.

In the optimization guide

What the optimization guide says about VPGATHERQQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Gathers and scatters: Where the layout of the data is known, vector loads and shuffles usually beat a gather.
• Gathers and scatters: Gathers beat scalar loads on Skylake, while AMD lists them as microcode on Zen 3, Zen 4 and Zen 5.

Crestmont and Gracemont

• Vectors and AVX2: Gathers are microcoded on these cores and take about 50 cycles.

Golden Cove and Raptor Cove

• Vectors, AVX-512 and AMX: A gather is a load micro-op for each element plus a few more: LLVM’s models give an eight-element VPGATHERDD 12 micro-ops and a latency of 30 cycles, and the 16-element one of Sapphire Rapids 19 micro-ops.

Haswell and Broadwell

• Gathers: Haswell is the first core with gathers, and each one runs as many micro-ops; Broadwell runs them much faster.

Skylake to Cooper Lake

• Vectors on all parts: Gathers are faster than on Broadwell and beat a sequence of scalar loads unless they fetch only two elements or the data comes from memory rather than the caches.

Zen 2

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, in AMD’s spreadsheet and LLVM’s model, so vector loads and shuffles beat them when the indices are known in advance.

Zen 3

• Vectors and floating point: Gathers such as VPGATHERDD are microcoded, and a register loaded in pieces is slower than one full-width load, so vector loads and shuffles beat both when the indices are known in advance.

Zen 4

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance, and a register loaded in pieces is slower than one full-width load.

Zen 5

• Vectors and floating point: A gather is slower than vector loads and shuffles when the indices are known in advance.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

x = mem.index.number
if x in (ymm1.number, ymm3.number):
    fault(UD)
if ymm1.number == ymm3.number:
    fault(UD)
for i in range(VL // 64):
    if ymm3.sq[i] < 0:
        a = mem.index.sq[i] * mem.scale
        ymm1.q[i] = load(mem.base + a, 64)
ymm3.write(0)
# ymm1 is zeroed from bit VL up

if mem.index.number == zmm1.number:
    fault(UD)
for i in range(VL // 64):
    if k1[i]:
        a = mem.index.sq[i] * mem.scale
        zmm1.q[i] = load(mem.base + a, 64)
k1.write(0)  # all of it
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-12

EVEX forms

AVX512-E12

Attributes

What else XED records about the forms. How to read.

All forms

gather

EVEX forms

write masking; memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPGATHERQQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPBROADCASTB
• VPBROADCASTD
• VPBROADCASTQ
• VPBROADCASTW
• VPCMPEQB
• VPCMPEQD
• VPCMPEQQ
• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB

All 138 AVX2 instructions

More AVX10.1 instructions

• VPERMPS
• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD

All 686 AVX10.1 instructions