VPHSUBSW instruction (AVX, AVX2)

Forms

Every encoding of VPHSUBSW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPHSUBSW xmm, xmm, m128` VPHSUBSW_XMMdq_XMMdq_MEMdq	`VEX.128.66.0F38.WIG 07 /r`	AVX
`VPHSUBSW xmm, xmm, xmm` VPHSUBSW_XMMdq_XMMdq_XMMdq	`VEX.128.66.0F38.WIG 07 /r`	AVX
`VPHSUBSW ymm, ymm, m256` VPHSUBSW_YMMqq_YMMqq_MEMqq	`VEX.256.66.0F38.WIG 07 /r`	AVX2
`VPHSUBSW ymm, ymm, ymm` VPHSUBSW_YMMqq_YMMqq_YMMqq	`VEX.256.66.0F38.WIG 07 /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Horizontal: adjacent pairs of words are combined, those of xmm2 into the low half of the result and those of xmm3 into the high half.

The ymm form repeats this in each 128-bit lane.

Result words 7 to 0: b6-b7, b4-b5, b2-b3, b0-b1, a6-a7, a4-a5, a2-a3, a0-a1.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    j = i - i % 8 + 2 * (i % 4)
    if i % 8 < 4:
        sa = ymm2.sw[j]
        sb = ymm2.sw[j + 1]
        ymm1.w[i] = ssat(sa - sb, 16)
    else:
        sa = src3.sw[j]
        sb = src3.sw[j + 1]
        ymm1.w[i] = ssat(sa - sb, 16)
# ymm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPHSUBSW xmm, xmm, xmm/m128` `VPHSUBSW ymm, ymm, ymm/m256`
`xmm, ymm`	explicit	write
`xmm, ymm`	explicit	read
`xmm/m128, ymm/m256`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-4

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPHSUBSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_hsubs_epi16` `__m128i _mm_hsubs_epi16(__m128i __a, __m128i __b)`	`VPHSUBSW xmm, xmm, xmm` VEX.128 -mavxwith AVX enabled
`_mm256_hsubs_epi16` `__m256i _mm256_hsubs_epi16(__m256i __a, __m256i __b)`	`VPHSUBSW ymm, ymm, ymm` VEX.256 -mavx2

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions