VPINSRB

VPINSRB is the VEX and EVEX form of PINSRB, whose page covers the immediate, building vectors of bytes and an index known only at run time. The other fifteen bytes come from a separate source register instead of the destination, and bits 128 and up are zeroed, so the result no longer waits for the destination’s old value. Only a 128-bit form exists: VEX.L = 1 or EVEX.L’L other than 0 raises #UD, and in 64-bit mode Intel’s table ignores VEX.W, as it ignores REX.W for PINSRB. The VEX form needs AVX; the EVEX form needs AVX512BW or AVX10.1, and adds only XMM16 to XMM31, with no mask.

On Zen 5, vpinsrb xmm8, xmm15, eax, 0xaf put FDh, the low byte of RAX, into byte 15 and took the other bytes from XMM15, and {evex} vpinsrb xmm0, xmm31, byte ptr [mem], 0x25 put the byte C5h from memory into byte 5 of a copy of XMM31; both cleared bits 511:128.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 compile v[5] = c on 16 unsigned chars to one VPINSRB, from a register or from memory. A byte in the upper half of a ymm register, v[20] = c, is extracted, inserted and put back with VEXTRACTI128, VPINSRB and VINSERTI128 in both compilers (GCC writes the 32X4 forms at -v4).

For _mm_setr_epi8 over 16 bytes loaded from scattered addresses, the two styles of PINSRB’s page carry over at -v3: Clang’s chain of 15 VPINSRBs after a MOVZX and VMOVD, and GCC’s eight pairs joined by unpacks. At -v4 Clang drops the chain: two masked VMOVDQU8 loads pick the bytes out of two 32-byte windows, and VPSHUFB and VPOR put them in order.

AMD’s latency spreadsheet for Zen 5 gives the register form two macro-ops on pipes FP1 or FP2, a latency of 2 cycles and one per cycle, and the memory form one macro-op, two per cycle, in its VEX and EVEX rows alike.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(xmm2.read())
xmm1.b[imm8 & 15] = src3.b[0]
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPINSRB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ

All 253 AVX instructions

More AVX10.1 instructions

• VPERMQ
• VPERMT2B
• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ

All 686 AVX10.1 instructions