VPINSRD instruction (AVX, AVX10.1)

VPINSRD is the VEX and EVEX form of PINSRD, whose page covers the immediate, the two ways compilers build a vector from four values, and Intel’s strided loads. The legacy form keeps the other three elements in the destination, which it therefore has to wait for; the newer encodings take them from a separate source register and zero bits 128 and up. Only a 128-bit form exists: VEX.L = 1 or EVEX.L’L other than 0 raises #UD. The VEX form needs AVX; the EVEX form needs AVX512DQ, not AVX512F, or AVX10.1, and adds only XMM16 to XMM31, with no mask. With W1 the same opcode is VPINSRQ.

On Zen 5, vpinsrd xmm4, xmm4, edx, 0xdf put B6978770h, EDX, into element 3 and kept the rest of XMM4, and {evex} vpinsrd xmm17, xmm30, dword ptr [mem], 0x87 put the four bytes from memory into element 3 of a copy of XMM30; both cleared bits 511:128.

In compiled code

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 compile v[2] = x on four unsigneds to one VPINSRD, and _mm_setr_epi32(a, b, c, d) as PINSRD’s page shows: Clang chains three VPINSRDs after a VMOVD, GCC builds two halves and joins them with VPUNPCKLQDQ. For element 6 of eight, GCC extracts, inserts and puts back with VEXTRACTI128, VPINSRD and VINSERTI128, while Clang broadcasts x with VPBROADCASTD and blends it in with VPBLENDD; at -v4 the broadcast reads EDI itself.

Gathering p[0], p[7], p[13] and p[29], GCC uses two VMOVD loads and two VPINSRDs from memory. Clang notices that the first two lie in one 32-byte window, takes them with one VPERMD of that window (at -v4 after a masked load), and inserts the other two with VPINSRD.

AMD’s latency spreadsheet for Zen 5 gives the register form two macro-ops on pipes FP0 to FP3, a latency of 1 cycle and one per cycle, and the memory form one macro-op, two per cycle, in its VEX and EVEX rows alike.

Forms

Every encoding of VPINSRD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPINSRD xmm, xmm, m32, imm8` VPINSRD_XMMdq_XMMdq_MEMd_IMMb	`VEX.128.66.0F3A.W0 22 /r ib`	AVX
`VPINSRD xmm, xmm, r32, imm8` VPINSRD_XMMdq_XMMdq_GPR32d_IMMb	`VEX.128.66.0F3A.W0 22 /r ib`	AVX
`VPINSRD xmm, xmm, r32, imm8` VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512	`EVEX.128.66.0F3A.W0 22 /r ib`	AVX10.1 or AVX512DQ
`VPINSRD xmm, xmm, m32, imm8` VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512	`EVEX.128.66.0F3A.W0 22 /r ib`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, xmm, m32, imm8`	`xmm, xmm, r32, imm8`	`xmm, xmm, r32, imm8`
Sandy Bridge	7 / 0.5p15	2 / 1p15
Haswell, Broadwell, Skylake	6 / 1p5	2 / 2p5
Skylake-SP	6 / 1p5	2 / 2p5	2 / 2p5
Ice Lake	6 / 0.5p15	2 / 1p15	2 / 1p15
Alder Lake	8 / 0.5p15	4 / 1p15
Sapphire Rapids	8 / 0.5p15	4 / 1p15	4 / 1p15
Lunar Lake	7 / 2V2 V3	5 / 1.33V2 V3 p1 p3 p5
Piledriver	6 / 2FPMAL FPU0 FPU1	12 / 1.5FPMAL FPU0 FPU1
Zen	8 / 0.5FPU0 FPU1 FPU2 FPU3	1 / 0.25FPU0 FPU1 FPU2 FPU3
Zen 2	8 / 0.33FPU0 FPU1 FPU2 FPU3	1 / 0.25FPU0 FPU1 FPU2 FPU3
Zen 3	8 / 1.5FP45 LSU Load	2 / 1FP45
Zen 4	8 / 1.5FP45 LSU Load	2 / 1FP45	1 / 1FP45
Jaguar	4 / 1FPU0 FPU1 VALU0 VALU1	7 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Insert: the doubleword from r32 replaces doubleword imm8 of xmm2; the rest of the result comes from xmm2.

Example: imm8 = 0x02.

With imm8 = 0x02, result doublewords 3 to 0: a3, b0, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(xmm2.read())
xmm1.d[imm8 & 3] = src3.d[0]
# xmm1 is zeroed from bit 128 up

Run on AMD Zen 5 (EPYC 9645): 4 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPINSRD xmm, xmm, r/m32, imm8`
`xmm`	explicit	write
`xmm`	explicit	read
`r/m32`	explicit	read
`imm8`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms: avx-type-5
EVEX forms: AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPINSRD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_insert_epi32` `__m128i _mm_insert_epi32(__m128i X, int I, const int N)`	`VPINSRD xmm, xmm, r32, imm8` VEX.128 -mavxwith AVX enabled

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX512DQ_128N` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

AVX512DQ_128N

AVX10.1

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

AVX512DQ
CPUID.(EAX=07H,ECX=0):EBX[17] AVX512DQ

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

In compiled code#