VPINSRQ

VPINSRQ is the VEX and EVEX form of PINSRQ, whose page covers building a vector from two 64-bit values. It is VPINSRD with W1 and follows that page’s rules: the kept half comes from a separate source register, bits 128 and up are zeroed, only a 128-bit form exists, and the EVEX form needs AVX512DQ or AVX10.1, adding only XMM16 to XMM31, with no mask. Only bit 0 of the immediate counts.

Outside 64-bit mode Intel’s entry says two things: its opcode table notes that VEX.W and EVEX.W are ignored there, which would make the instruction VPINSRD, and its description says that VPINSRQ raises #UD there.

On Zen 5, vpinsrq xmm12, xmm6, rsi, 0xcf, with bit 0 set, put RSI in the high quadword and the low quadword of XMM6 below it; vpinsrq xmm12, xmm6, qword ptr [mem], 0xa0, with bit 0 clear, put the eight bytes from memory in the low quadword instead; and {evex} vpinsrq xmm0, xmm31, qword ptr [mem], 0x73 kept the low quadword of XMM31. All three cleared bits 511:128.

In compiled code#

In our builds at -O2 with -march=x86-64-v3 and x86-64-v4, GCC 14 and Clang 23 compile v[1] = x on two long longs to one VPINSRQ. The two styles of PINSRQ’s page remain for _mm_set_epi64x: GCC uses VMOVQ and VPINSRQ, Clang two VMOVQs and VPUNPCKLQDQ, and for four values each builds two halves that way and joins them with VINSERTI128. For v[3] = x on four, GCC extracts the upper half, inserts and puts it back, while Clang broadcasts x with VPBROADCASTQ and blends it in with VPBLENDD.

AMD’s latency spreadsheet for Zen 5 gives the register form two macro-ops on pipes FP0 to FP3, a latency of 1 cycle and one per cycle, and the memory form one macro-op, two per cycle, in its VEX and EVEX rows alike.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(xmm2.read())
xmm1.q[imm8 & 1] = src3.q[0]
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPINSRQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPCMPGTQ
• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ

All 253 AVX instructions

More AVX10.1 instructions

• VPERMT2D
• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB

All 686 AVX10.1 instructions