VPINSRW

VPINSRW puts the low word of a 32-bit general-purpose register, or a word of memory, into one element of an XMM register: the VEX and EVEX form of PINSRW, whose page covers the immediate and the ways compilers build vectors of words. The other seven words come from a separate source register rather than from the destination, and bits 128 and up are zeroed. Both forms are 128-bit only: AVX gives the VEX form, and AVX512BW or AVX10.1 the EVEX form, which adds only XMM16 to XMM31, with no write mask. On Zen 5, vpinsrw xmm7, xmm11, esi, 0xcb put 29BBh, the low word of RSI, into word 3, the low three bits of CBh, and took the rest from XMM11, and {evex} vpinsrw xmm9, xmm9, word ptr [mem], 0xe7 put 00C5h into word 7.

In compiled code#

In our builds at -O2, GCC 14 and Clang 23 compile v[3] = x on a vector of eight shorts to one VPINSRW with -march=x86-64-v3 and -march=x86-64-v4, from a register or from memory. A word in a ymm register cannot be inserted directly: for v[11] = x, GCC extracts the upper half with VEXTRACTI128, inserts and puts it back with VINSERTI128, while Clang broadcasts x with VPBROADCASTW and blends it in with VPBLENDW and VPBLENDD.

For _mm_setr_epi16 over eight arguments, GCC keeps its four independent pairs joined by unpacks, and Clang a chain of seven VPINSRW after a VMOVD, also for eight words loaded from scattered addresses at -v3. At -v4 Clang loads those eight with four zero-masked VMOVDQU16, each picking two words of a 32-byte window, and joins them with VPERMI2W.

AMD’s latency spreadsheet for Zen 5 gives the register form two macro-ops, one cycle, one per cycle, and the memory form one macro-op, two per cycle, in its VEX and EVEX rows alike.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

xmm1.write(xmm2.read())
xmm1.w[imm8 & 7] = src3.w[0]
# xmm1 is zeroed from bit 128 up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E9NF

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPINSRW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPCMPGTW
• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD

All 253 AVX instructions

More AVX10.1 instructions

• VPERMT2PD
• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD

All 686 AVX10.1 instructions