VPLZCNTD

VPLZCNTD counts the zero bits above the highest set bit of each doubleword, as LZCNT does for one register: 0 for an element with its top bit set, 32 for a zero element. Every input has a defined result. It belongs to AVX512CD, part of x86-64-v4, and VPLZCNTQ counts in quadwords; there is no byte or word form.

In compiled code#

With -march=x86-64-v4, Clang 23 at -O2 vectorizes a loop of __builtin_clz into VPLZCNTD, and since the zero case is defined, also a ? __builtin_clz(a) : 32 and 32 - __builtin_clzg(a, 32), the bit width of each element; GCC 14 keeps such loops scalar with LZCNT, but emits VPLZCNTD for the same operations applied to the elements of a vector type. With only AVX2 there is no per-element count, and the same eight __builtin_clzg cost Clang 19 instructions.

Counting trailing zeros needs no instruction of its own: (x - 1) & ~x sets exactly the bits below the lowest set bit, and 32 minus their leading-zero count is the trailing-zero count. Both compilers compile a vector of __builtin_ctzg(x, 32) to that sequence, a VPADDD of -1, VPANDN, VPLZCNTD and a subtraction from 32.

With VPCONFLICTD#

Intel’s optimization manual pairs it with VPCONFLICTD (Section 17.16.1): the conflict result of an element has bit j set for each equal element j below it, so 31 minus its leading-zero count is the position of the nearest equal element, and -1 where there is none. That vector serves as the index of VPERMD to bring each element the value it must be combined with (Figure 17-15, Example 17-24).

AMD’s Zen 5 guide lists VPLZCNTD as one macro-op with a latency of 2 cycles on XMM, YMM and ZMM registers alike.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        zmm1.d[i] = lzcnt(src2.d[i], 32)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src2.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPLZCNTD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPERMT2PS
• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ

All 686 AVX10.1 instructions