VPLZCNTQ

VPLZCNTQ counts the zero bits above the highest set bit of each quadword, as LZCNT does for one 64-bit register: 0 for an element with its top bit set, 64 for a zero element. It is the quadword form of VPLZCNTD, whose page shows how the count gives trailing zeros and how it turns a VPCONFLICTQ result into the position of the nearest equal element. It belongs to AVX512CD, takes a write mask and a broadcast quadword, and needs AVX512VL below 512 bits.

Recorded on Zen 5#

• The ends. vplzcntq zmm1{k3}, zmm2 gave 0 for 8000000000000000h, 1 for 7FFFFFFFFFFFFFFFh, 40h for 0 and 3Ch for 0Fh, in the elements K3 selects.
• Broadcast. A broadcast 1 gave 3Fh, 63, in every selected element.
• Zeroing. vplzcntq ymm0{k5}{z}, ymm31 with only bit 0 of the four set wrote 3Fh for 1 and zeroed the other three elements and the register from bit 256 up.

In compiled code#

At -O2 with -march=x86-64-v4, both compilers vectorize a loop of __builtin_clzg(a[i], 64) over uint64_t arrays with VPLZCNTQ, GCC 14 on ZMM registers with the operand in memory and Clang 23 on YMM registers. For __builtin_ctzg(a[i], 64) both use the sequence of VPLZCNTD’s page in 64 bits: VPADDQ of -1, VPANDNQ, VPLZCNTQ and a VPSUBQ from 64. _mm512_lzcnt_epi64 is one VPLZCNTQ.

AMD’s Zen 5 latency spreadsheet gives one macro-op with 2 cycles at every width, two per cycle on pipes FP0 and FP3, as for VPLZCNTD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        zmm1.q[i] = lzcnt(src2.q[i], 64)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src2.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPLZCNTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPERMT2Q
• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW

All 686 AVX10.1 instructions