x86-64.net

Instruction

VPLZCNTQ

Counts the leading zero bits of each quadword.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPLZCNTQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPLZCNTQ zmm {k}{z}, zmm VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CDEVEX.512.66.0F38.W1 44 /rAVX10.1 or AVX512CD
VPLZCNTQ zmm {k}{z}, m512/m64bcst VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CDEVEX.512.66.0F38.W1 44 /rAVX10.1 or AVX512CD
VPLZCNTQ xmm {k}{z}, xmm VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512EVEX.128.66.0F38.W1 44 /rAVX10.1 or AVX512CD + AVX512VL
VPLZCNTQ xmm {k}{z}, m128/m64bcst VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512EVEX.128.66.0F38.W1 44 /rAVX10.1 or AVX512CD + AVX512VL
VPLZCNTQ ymm {k}{z}, ymm VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512EVEX.256.66.0F38.W1 44 /rAVX10.1 or AVX512CD + AVX512VL
VPLZCNTQ ymm {k}{z}, m256/m64bcst VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512EVEX.256.66.0F38.W1 44 /rAVX10.1 or AVX512CD + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPLZCNTQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_lzcnt_epi64 __m128i _mm_lzcnt_epi64(__m128i __A)

VPLZCNTQ xmm, xmm EVEX.128 -mavx512vl -mavx512cd

_mm_mask_lzcnt_epi64 __m128i _mm_mask_lzcnt_epi64(__m128i __W, __mmask8 __U, __m128i __A)

VPLZCNTQ xmm {k}, xmm EVEX.128 -mavx512vl -mavx512cd

_mm_maskz_lzcnt_epi64 __m128i _mm_maskz_lzcnt_epi64(__mmask8 __U, __m128i __A)

VPLZCNTQ xmm {k}{z}, xmm EVEX.128 -mavx512vl -mavx512cd

_mm256_lzcnt_epi64 __m256i _mm256_lzcnt_epi64(__m256i __A)

VPLZCNTQ ymm, ymm EVEX.256 -mavx512vl -mavx512cd

_mm256_mask_lzcnt_epi64 __m256i _mm256_mask_lzcnt_epi64(__m256i __W, __mmask8 __U, __m256i __A)

VPLZCNTQ ymm {k}, ymm EVEX.256 -mavx512vl -mavx512cd

_mm256_maskz_lzcnt_epi64 __m256i _mm256_maskz_lzcnt_epi64(__mmask8 __U, __m256i __A)

VPLZCNTQ ymm {k}{z}, ymm EVEX.256 -mavx512vl -mavx512cd

_mm512_lzcnt_epi64 __m512i _mm512_lzcnt_epi64(__m512i __A)

VPLZCNTQ zmm, zmm EVEX.512 -mavx512cd

_mm512_mask_lzcnt_epi64 __m512i _mm512_mask_lzcnt_epi64(__m512i __W, __mmask8 __U, __m512i __A)

VPLZCNTQ zmm {k}, zmm EVEX.512 -mavx512cd

_mm512_maskz_lzcnt_epi64 __m512i _mm512_maskz_lzcnt_epi64(__mmask8 __U, __m512i __A)

VPLZCNTQ zmm {k}{z}, zmm EVEX.512 -mavx512cd

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512CD_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512CD
CPUID.(EAX=07H,ECX=0):EBX[28] AVX512CD

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512CD_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512CD + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[28] AVX512CD
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512CD_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512CD + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[28] AVX512CD
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.