VPMADD52HUQ

VPMADD52HUQ is the other half of VPMADD52LUQ: it multiplies the low 52 bits of each quadword of its two sources and adds bits 103 to 52 of the 104-bit product, where VPMADD52LUQ adds bits 51 to 0, to the quadword in the destination. That page explains the radix-2^52 arithmetic the pair serves, the AVX512_IFMA and AVX-IFMA forms and the build-flag trap of the VEX encoding; on Zen 5 the VEX forms of VPMADD52HUQ raised #UD as well.

The high half in recorded cases#

• One factor all ones. In vpmadd52huq ymm7{k2}{z}, ymm12, ymm7 element 0 of YMM7 was both accumulator and factor, D05154C465A0A03Ch, and YMM12’s was FFFFFFFFFFFFFFFFh, whose low 52 bits are 2^52 - 1. The high half of the product was the other factor’s low 52 bits, 154C465A0A03Ch, less one, and the element became D052A988CB414077h.
• Small products add nothing. With a broadcast factor of 80h, vpmadd52huq zmm17{k3}, zmm30, qword bcst [mem] left an accumulator unchanged where the other factor was 1, and also where it was 8000000000000000h, whose low 52 bits are zero.
• The sum wraps. In the same case, factors of all ones added 7Fh: FFFFFFFFFFFFFFFFh became 7Eh and 7FFFFFFFFFFFFFFFh became 800000000000007Eh, with no saturation and no flag.

In compiled code#

GCC 14 and Clang 23 at -O2 with -march=znver5 do not find the instruction in a[i] += ((unsigned __int128)(b[i] & M) * (c[i] & M)) >> 52 over uint64_t arrays, with M = 2^52 - 1. GCC keeps the loop scalar with MULX and SHRD; Clang vectorizes the masking and the addition but moves every element to a general register for its MULX and SHRD and back. The intrinsics _mm512_madd52hi_epu64 and kin give VPMADD52HUQ, and a function that applies both halves to the same factors gets one VPMADD52LUQ and one VPMADD52HUQ from either compiler.

AMD’s Zen 5 latency spreadsheet gives VPMADD52HUQ what it gives VPMADD52LUQ: 4 cycles and two per cycle on pipes FP0 and FP1. Zen 5’s 10 recorded cases cover the VEX forms, which all faulted, and the EVEX register, memory and broadcast forms at all three widths.

In the optimization guide

What the optimization guide says about VPMADD52HUQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont runs the 52-bit integer multiply-adds of AVX-IFMA in its floating-point multipliers.

Ice Lake to Rocket Lake

• Vectors and AVX-512: VPMADD52LUQ and VPMADD52HUQ multiply eight pairs of 52-bit numbers and add the low or the high 52 bits of each product to a 64-bit accumulator, for the big-number arithmetic of RSA.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 23 & 1:
    fault(UD)  # CPUID: no AVX-IFMA
for i in range(VL // 64):
    a = ymm1.q[i]
    b = ymm2.q[i]
    c = src3.q[i]
    x = low(b, 52) * low(c, 52)
    ymm1.q[i] = a + (x >> 52)
# ymm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:
        a = zmm1.q[i]
        b = zmm2.q[i]
        c = src3.q[i]
        x = low(b, 52) * low(c, 52)
        zmm1.q[i] = a + (x >> 52)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMADD52HUQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-IFMA instructions

• VPMADD52LUQ

More AVX10.1 instructions

• VPERMT2W
• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M

All 686 AVX10.1 instructions