x86-64.net

Instruction

VPMADD52HUQ

Multiplies the low 52 bits of packed unsigned quadwords into 104-bit products and adds the high 52 bits of each product to a 64-bit accumulator.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPMADD52HUQ that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMADD52HUQ xmm, xmm, xmm VPMADD52HUQ_XMMu64_XMMu64_XMMu64VEX.128.66.0F38.W1 B5 /rAVX_IFMA
VPMADD52HUQ xmm, xmm, m128 VPMADD52HUQ_XMMu64_XMMu64_MEMu64VEX.128.66.0F38.W1 B5 /rAVX_IFMA
VPMADD52HUQ ymm, ymm, ymm VPMADD52HUQ_YMMu64_YMMu64_YMMu64VEX.256.66.0F38.W1 B5 /rAVX_IFMA
VPMADD52HUQ ymm, ymm, m256 VPMADD52HUQ_YMMu64_YMMu64_MEMu64VEX.256.66.0F38.W1 B5 /rAVX_IFMA
VPMADD52HUQ xmm {k}{z}, xmm, xmm VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512EVEX.128.66.0F38.W1 B5 /rAVX10.1 or AVX512IFMA + AVX512VL
VPMADD52HUQ xmm {k}{z}, xmm, m128/m64bcst VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512EVEX.128.66.0F38.W1 B5 /rAVX10.1 or AVX512IFMA + AVX512VL
VPMADD52HUQ ymm {k}{z}, ymm, ymm VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512EVEX.256.66.0F38.W1 B5 /rAVX10.1 or AVX512IFMA + AVX512VL
VPMADD52HUQ ymm {k}{z}, ymm, m256/m64bcst VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512EVEX.256.66.0F38.W1 B5 /rAVX10.1 or AVX512IFMA + AVX512VL
VPMADD52HUQ zmm {k}{z}, zmm, zmm VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512EVEX.512.66.0F38.W1 B5 /rAVX10.1 or AVX512IFMA
VPMADD52HUQ zmm {k}{z}, zmm, m512/m64bcst VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512EVEX.512.66.0F38.W1 B5 /rAVX10.1 or AVX512IFMA

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMADD52HUQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_madd52hi_avx_epu64 __m128i _mm_madd52hi_avx_epu64(__m128i __X, __m128i __Y, __m128i __Z)

VPMADD52HUQ xmm, xmm, xmm VEX.128 -mavxifma

_mm_madd52hi_epu64 __m128i _mm_madd52hi_epu64(__m128i X, __m128i Y, __m128i Z)

VPMADD52HUQ xmm, xmm, xmm EVEX.128 -mavx512ifma -mavx512vl

_mm_mask_madd52hi_epu64 __m128i _mm_mask_madd52hi_epu64(__m128i __W, __mmask8 __M, __m128i __X, __m128i __Y)

VPMADD52HUQ xmm {k}, xmm, xmm EVEX.128 -mavx512ifma -mavx512vl

_mm_maskz_madd52hi_epu64 __m128i _mm_maskz_madd52hi_epu64(__mmask8 __M, __m128i __X, __m128i __Y, __m128i __Z)

VPMADD52HUQ xmm {k}{z}, xmm, xmm EVEX.128 -mavx512ifma -mavx512vl

_mm256_madd52hi_avx_epu64 __m256i _mm256_madd52hi_avx_epu64(__m256i __X, __m256i __Y, __m256i __Z)

VPMADD52HUQ ymm, ymm, ymm VEX.256 -mavxifma

_mm256_madd52hi_epu64 __m256i _mm256_madd52hi_epu64(__m256i X, __m256i Y, __m256i Z)

VPMADD52HUQ ymm, ymm, ymm EVEX.256 -mavx512ifma -mavx512vl

_mm256_mask_madd52hi_epu64 __m256i _mm256_mask_madd52hi_epu64(__m256i __W, __mmask8 __M, __m256i __X, __m256i __Y)

VPMADD52HUQ ymm {k}, ymm, ymm EVEX.256 -mavx512ifma -mavx512vl

_mm256_maskz_madd52hi_epu64 __m256i _mm256_maskz_madd52hi_epu64(__mmask8 __M, __m256i __X, __m256i __Y, __m256i __Z)

VPMADD52HUQ ymm {k}{z}, ymm, ymm EVEX.256 -mavx512ifma -mavx512vl

_mm512_madd52hi_epu64 __m512i _mm512_madd52hi_epu64(__m512i __X, __m512i __Y, __m512i __Z)

VPMADD52HUQ zmm, zmm, zmm EVEX.512 -mavx512ifma

_mm512_mask_madd52hi_epu64 __m512i _mm512_mask_madd52hi_epu64(__m512i __W, __mmask8 __M, __m512i __X, __m512i __Y)

VPMADD52HUQ zmm {k}, zmm, zmm EVEX.512 -mavx512ifma

_mm512_maskz_madd52hi_epu64 __m512i _mm512_maskz_madd52hi_epu64(__mmask8 __M, __m512i __X, __m512i __Y, __m512i __Z)

VPMADD52HUQ zmm {k}{z}, zmm, zmm EVEX.512 -mavx512ifma

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX_IFMA

AVX_IFMA
CPUID.(EAX=07H,ECX=1):EAX[23] AVX_IFMA

Arrow Lake, Panther Lake, Nova Lake, Diamond Rapids, Sierra Forest, Clearwater Forest
AVX512_IFMA_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512IFMA + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[21] AVX512IFMA
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_IFMA_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512IFMA + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[21] AVX512IFMA
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512_IFMA_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512IFMA
CPUID.(EAX=07H,ECX=0):EBX[21] AVX512IFMA

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX-IFMA instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-092, June 2026)
  4. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.