VPMADD52LUQ

VPMADD52LUQ multiplies the low 52 bits of each quadword of its two sources, which gives an unsigned product of up to 104 bits, and adds the low 52 bits of that product to the quadword already in the destination. VPMADD52HUQ adds bits 103 to 52 instead. The two together multiply big integers stored in radix 2^52: each quadword holds a 52-bit digit, the pair adds both halves of every partial product into accumulators, and the 12 spare bits of each accumulator hold the carries of up to 4,096 such additions until a later pass propagates them. Intel’s optimization guide names modular exponentiation for RSA as the purpose, as used in OpenSSL (Section 19.4).

What is ignored and what wraps#

Bits 63 to 52 of both multiplicands are ignored, but the accumulator is the whole quadword, and the addition wraps modulo 2^64 without saturating or setting any flag. In a case recorded on Zen 5, an accumulator of FFFFFFFFFFFFFFFFh plus a product of 597B1E8E4176Eh gave 597B1E8E4176Dh.

The low half on its own is just the product modulo 2^52, so compilers can build it from an ordinary multiply. For a[i] += ((b[i] & M) * (c[i] & M)) & M with M = 2^52 - 1, GCC 14 and Clang 23 at -O2 with -march=znver5 emit VPMULLQ, VPANDQ and VPADDQ (Clang drops the masks on the inputs, which cannot change the low 52 bits), never VPMADD52LUQ: it comes from the intrinsic _mm512_madd52lo_epu64 and its kin.

Two extensions#

AVX512_IFMA has the EVEX forms, with masking, broadcast and 512-bit vectors. AVX-IFMA has VEX forms for xmm and ymm only, which Intel’s guide introduces with the Crestmont cores (Section 4.1.8.2). Zen 5 has the first and not the second: its CPUID reports no AVX-IFMA, and every case recorded with a VEX form raised #UD. That is a trap in build flags: with -march=znver5 -mavxifma, GCC 14 and Clang 23 encode the AVX-512 intrinsic _mm256_madd52lo_epu64 as the shorter {vex} vpmadd52luq, so the program faults on Zen 5. The VEX intrinsic is _mm256_madd52lo_avx_epu64.

AMD’s Zen 5 guide lists VPMADD52LUQ as one macro-op with a latency of 4 cycles.

In the optimization guide

What the optimization guide says about VPMADD52LUQ, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: Crestmont runs the 52-bit integer multiply-adds of AVX-IFMA in its floating-point multipliers.

Ice Lake to Rocket Lake

• Vectors and AVX-512: VPMADD52LUQ and VPMADD52HUQ multiply eight pairs of 52-bit numbers and add the low or the high 52 bits of each product to a 64-bit accumulator, for the big-number arithmetic of RSA.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

if not cpuid_leaf(7, 1)[0] >> 23 & 1:
    fault(UD)  # CPUID: no AVX-IFMA
for i in range(VL // 64):
    a = ymm1.q[i]
    b = ymm2.q[i]
    c = src3.q[i]
    x = low(b, 52) * low(c, 52)
    ymm1.q[i] = a + low(x, 52)
# ymm1 is zeroed from bit VL up

for i in range(VL // 64):
    if k1[i]:
        a = zmm1.q[i]
        b = zmm2.q[i]
        c = src3.q[i]
        x = low(b, 52) * low(c, 52)
        zmm1.q[i] = a + low(x, 52)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMADD52LUQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX-IFMA instructions

• VPMADD52HUQ

More AVX10.1 instructions

• VPERMW
• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M

All 686 AVX10.1 instructions