VPMADDUBSW

VPMADDUBSW multiplies bytes in pairs and adds each two neighbouring products into a word: the bytes of the first source are read as unsigned, those of the second as signed, and each word of the result is a0*b0 + a1*b1, saturated to the signed 16-bit range. It is the VEX and EVEX form of SSSE3’s PMADDUBSW: VEX for xmm registers with AVX and ymm with AVX2, EVEX with AVX512BW for zmm registers, write masks and 32 registers, without embedded broadcast.

Mixed signs and saturation#

The operand order matters: swapping the sources reads every byte with the other signedness. One product ranges from -32,640 (255 times -128) to 32,385 (255 times 127), so the sum of two can leave the range of a word, and it is clamped to -32,768 or 32,767 without any flag. In a case recorded on Zen 5, the bytes 205 and 161 times -120 and -127 summed to -45,047 and gave -32,768. With small multipliers nothing saturates: a second source of ones adds neighbouring unsigned bytes into words, and multipliers 10 and 1 turn pairs of decimal digits into numbers from 0 to 99.

In quantized inference#

Before VNNI, 8-bit inference took VPMADDUBSW with unsigned activations as the first source and signed weights as the second, then VPMADDWD with ones and VPADDD to reach 32-bit sums. VPDPBUSD fuses the three, and Intel’s optimization manual notes that it is also more accurate, since nothing saturates at 16 bits (Section 8.2.1). Because only the first operand is unsigned, the manual handles signed activations by adding 128 to them and taking 128 times the sum of the weights back out of the bias (Section 8.3.2.3).

In compiled code#

For a loop that computes a[2*i]*b[2*i] + a[2*i+1]*b[2*i+1] from uint8_t a and int8_t b and clamps it to the range of int16_t, Clang 23 at -O2 recognizes the whole operation, saturation included, and emits VPMADDUBSW with -march=x86-64-v3 or -march=znver5; with -march=x86-64-v4 it widens to words instead. GCC 14 widens the bytes and multiplies with VPMULLW.

AMD’s Zen 5 guide lists VPMADDUBSW as one macro-op with a latency of 3 cycles on every register width, as for VPMADDWD.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.b[j] * src3.sb[j]
    if k1[i]:  # 1 without a write mask
        zmm1.w[i] = ssat(x, 16)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMADDUBSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPCMPISTRI
• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ

All 253 AVX instructions

More AVX2 instructions

• VPCMPEQW
• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPEXPANDB
• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB

All 686 AVX10.1 instructions