VPMADDWD

VPMADDWD multiplies signed words and adds each pair of neighboring products into a doubleword: the VEX and EVEX form of SSE2’s PMADDWD, whose page covers dot products and the one input that overflows, four words of 8000h. The newer forms write a separate destination, read memory at any alignment and zero the register above the vector length; since each pair stays inside its own doubleword, the wider registers simply hold more pairs. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and add a write mask with one bit per doubleword result, but no broadcast. On Zen 5:

• vpmaddwd xmm1, xmm2, xmm3 gave FFFFFFFFh, that is -1, for 7FFFh times 1 plus 8000h times 1, and 7FFF0001h for 8000h times 8000h plus 7FFFh times 7FFFh, the largest sum short of the overflow.
• vpmaddwd ymm24{k7}{z}, ymm3, ymm3 wrote the five doublewords whose bits are set in E3h, the low byte of K7, and zeroed the other three.

Dot products in our builds#

In our builds at -O2 over fixed-size int16_t arrays, s += a[i] * b[i] is VPMADDWD feeding VPADDD in GCC 14 and in Clang 23. GCC works on ymm registers with -march=x86-64-v3 and on zmm with -v4; Clang multiplies 16 bytes at a time at both levels and adds the results into ymm accumulators, and 32 bytes at a time with -march=znver5. With that option GCC uses VPDPWSSD instead, which folds the addition into the same instruction.

Written out by hand, d[i] = a[2*i] * b[2*i] + a[2*i+1] * b[2*i+1] is one VPMADDWD per vector in Clang. GCC first separates the even and odd words, with shifts and packs at -v3 and VPERMT2W at -v4, then multiplies them with VPMULLW and VPMULHW at -v3, or widens them with VPMOVSXWD and multiplies with VPMULLD at -v4, and adds the products. VPMULHW’s page shows Clang’s other use of it: full 32-bit products of words, each zero-extended so that it pairs with a zero.

AMD’s latency spreadsheet for Zen 5 gives the VEX row and the EVEX row alike a latency of 3 cycles, two per cycle on pipes FP0 and FP1.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    x = 0
    for j in range(2 * i, 2 * i + 2):
        x += zmm2.sw[j] * src3.sw[j]
    if k1[i]:  # 1 without a write mask
        zmm1.d[i] = x
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4NF

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMADDWD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPCMPISTRM
• VPERM2F128
• VPERMILPD
• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD

All 253 AVX instructions

More AVX2 instructions

• VPCMPGTB
• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPEXPANDD
• VPEXPANDQ
• VPEXPANDW
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW

All 686 AVX10.1 instructions