VPMASKMOVD

VPMASKMOVD is AVX2’s integer twin of VMASKMOVPS: it loads or stores the doublewords of an XMM or YMM register only where the top bit of the matching element of a mask register is set. A load writes zero to the other elements, and a store leaves the memory under them as it was. The bits moved are the same as VMASKMOVPS’s; the two differ in the extension they need (AVX2 rather than AVX) and in whether the data is meant for integer or floating-point instructions next. VPMASKMOVQ does the same with quadwords.

A mask from an integer compare, VPCMPEQD or VPCMPGTD, has all 32 bits of each element set or clear and can be used directly. Whether masked-off elements can fault is where the manuals part: Intel’s says they never do, AMD’s leaves it to the implementation (see VMASKMOVPS, with the costs Intel’s optimization manual lists for both instructions in Section 15.9).

In compiled code#

GCC 14 and Clang 23 at -O2 with -mavx2:

• if (c[i]) a[i] = b[i] over int arrays: both compare c with zero by VPCMPEQD and invert the result (GCC with a second VPCMPEQD against zero, Clang with VPXOR of all ones), then load b and store a with VPMASKMOVD, so that elements the condition rules out are neither read nor written. GCC first skips blocks whose mask is all zero with VPTEST.
• a[i] = c[i] ? b[i] : 0: both load b with VPMASKMOVD and store the result with a plain VMOVDQU. Clang relies on the zeros the masked load writes; GCC also clears those elements again with VPANDN.

A masked load or store also handles the last elements of a loop whose count is not a multiple of eight, with a mask from comparing a vector of element numbers 0 to 7 against the number left. Neither compiler does that at -O2: Clang finishes such a loop with scalar code, and GCC leaves a loop of unknown count scalar altogether.

With AVX-512 the same jobs go to VMOVDQU32 under a mask register. With -mavx512f, Clang builds the condition with VPTESTMD and GCC with VPCMPD, and both load and store with masked VMOVDQU32; GCC’s skip of empty blocks becomes KORTESTW.

In the optimization guide

What the optimization guide says about VPMASKMOVD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Vectors

• Masks and masked memory access: AVX’s VMASKMOV loads and stores can take assists of hundreds of cycles on Intel’s cores and are slow stores on Zen 3 and Zen 4.

Crestmont and Gracemont

• Vectors and AVX2: Masked loads and stores run one every two cycles on 256 bits, slower when a masked-off element would fault.

Zen 2

• Vectors and floating point: A masked load with VPMASKMOVD or vpmaskmovq is one or two macro-ops, but the masked store is microcoded, in AMD’s spreadsheet and in LLVM’s model. sources differ

Forms

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if ymm2.d[i] >> 31:
        ymm1.d[i] = mem.d[i]
    else:
        ymm1.d[i] = 0
# ymm1 is zeroed from bit VL up

for i in range(VL // 32):
    if ymm2.d[i] >> 31:  # the sign bit of the element
        mem.d[i] = ymm3.d[i]
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

avx-type-6

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMASKMOVD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX2 instructions

• VPCMPGTD
• VPCMPGTQ
• VPCMPGTW
• VPERM2I128
• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ

All 138 AVX2 instructions