x86-64.net

Instruction

VPMAXSB

Returns the larger of each pair of signed bytes.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMAXSB keeps the larger of each pair of bytes, compared as signed integers: the VEX and EVEX form of SSE4.1’s PMAXSB, whose page covers the operation and its uses, ReLU, clamping and reductions among them. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms belong to AVX512BW and add masking and the 512-bit width, with no broadcast for bytes. Every form writes a separate destination, zeroes it above the vector length and takes memory at any alignment. On Zen 5, the recorded vpmaxsb ymm4, ymm4, ymmword ptr [mem] kept 7Fh over 01h, 01h over 80h and FFh over 80h, -1 over -128, in both 128-bit lanes, and vpmaxsb xmm17{k2}{z}, xmm30, xmmword ptr [mem] wrote maxima into the nine bytes k2 selects and zeroed the rest.

In compiled code

In our builds at -O2 over int8_t arrays, b[i] > c[i] ? b[i] : c[i] is one VPMAXSB per vector with its second operand in memory, in GCC 14 and Clang 23 with -march=x86-64-v3; with -march=x86-64-v4 GCC moves to zmm registers and Clang stays with ymm. Two more cases:

  • A condition. if (u[i]) a[i] = max(b[i], c[i]) stays a scalar loop with CMOVL in GCC at -v3, and Clang stores byte by byte with VPEXTRB under branches; at -v4 both compute VPMAXSB over every byte and store under a byte mask with VMOVDQU8.
  • The largest element. GCC folds the array into one register with VPMAXSB and halves it, with VEXTRACTI128 at -v3 or VEXTRACTI64X4 and VEXTRACTI32X4 at -v4, then VPSRLDQ by 8, 4, 2 and 1. Clang flips the order with a VPXOR against 7Fh and lets VPHMINPOSUW finish, as for SSE4.1.

VPMINSB is its partner. AMD’s latency spreadsheet for Zen 5 gives VPMAXSB, VEX or EVEX, one cycle, four per cycle on any of pipes FP0 to FP3.

Forms

Every encoding of VPMAXSB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMAXSB xmm, xmm, m128 VPMAXSB_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 3C /rAVX
VPMAXSB xmm, xmm, xmm VPMAXSB_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 3C /rAVX
VPMAXSB ymm, ymm, m256 VPMAXSB_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 3C /rAVX2
VPMAXSB ymm, ymm, ymm VPMAXSB_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 3C /rAVX2
VPMAXSB xmm {k}{z}, xmm, xmm VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512EVEX.128.66.0F38.WIG 3C /rAVX10.1 or AVX512BW + AVX512VL
VPMAXSB xmm {k}{z}, xmm, m128 VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512EVEX.128.66.0F38.WIG 3C /rAVX10.1 or AVX512BW + AVX512VL
VPMAXSB ymm {k}{z}, ymm, ymm VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512EVEX.256.66.0F38.WIG 3C /rAVX10.1 or AVX512BW + AVX512VL
VPMAXSB ymm {k}{z}, ymm, m256 VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512EVEX.256.66.0F38.WIG 3C /rAVX10.1 or AVX512BW + AVX512VL
VPMAXSB zmm {k}{z}, zmm, zmm VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512EVEX.512.66.0F38.WIG 3C /rAVX10.1 or AVX512BW
VPMAXSB zmm {k}{z}, zmm, m512 VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512EVEX.512.66.0F38.WIG 3C /rAVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128no mask		xmm, xmm, xmm
xmm {k}{z}, xmm, xmmno mask
ymm {k}{z}, ymm, ymmno mask		ymm, ymm, m256
ymm {k}{z}, ymm, m256no mask		ymm, ymm, ymmxmm {k}{z}, xmm, xmmwith a mask, zeroing
ymm {k}{z}, ymm, ymmwith a mask, zeroing		xmm {k}{z}, xmm, m128with a mask, zeroingymm {k}{z}, ymm, m256with a mask, zeroingzmm {k}{z}, zmm, zmmno maskzmm {k}{z}, zmm, zmmwith a mask, zeroingzmm {k}{z}, zmm, m512no maskzmm {k}{z}, zmm, m512with a mask, zeroing
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p011 / 0.5p017 / 0.5p018 / 0.5p011 / 1p01 / 1p08 / 1p08 / 1p0
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p013 / 0.5p0111 / 0.5p0111 / 0.5p011 / 1p03 / 1p09 / 1p011 / 1p0
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each byte of the result comes from the byte in the same place in each source.
VPMAXSB: element by elementResult byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.…01234567xmm2a11111110k1…r0r1r2r3r4r5r7xmm1…01234567xmm3or m128b

Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result byte i comes from byte i of xmm2 and xmm3. Result bytes 7 to 0: r7, unchanged (bit 6 of k1 is 0), r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        sa = zmm2.sb[i]
        sb = src3.sb[i]
        zmm1.b[i] = max(sa, sb)
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMAXSB xmm, xmm, xmm/m128 VPMAXSB ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPMAXSB xmm {k}{z}, xmm, xmm/m128 VPMAXSB ymm {k}{z}, ymm, ymm/m256 VPMAXSB zmm {k}{z}, zmm, zmm/m512
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128, ymm/m256, zmm/m512explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMAXSB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_max_epi8 __m128i _mm_max_epi8(__m128i __V1, __m128i __V2)

VPMAXSB xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_max_epi8 __m128i _mm_mask_max_epi8(__m128i __W, __mmask16 __M, __m128i __A, __m128i __B)

VPMAXSB xmm {k}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm_maskz_max_epi8 __m128i _mm_maskz_max_epi8(__mmask16 __M, __m128i __A, __m128i __B)

VPMAXSB xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl -mavx512bw

_mm256_max_epi8 __m256i _mm256_max_epi8(__m256i __a, __m256i __b)

VPMAXSB ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_max_epi8 __m256i _mm256_mask_max_epi8(__m256i __W, __mmask32 __M, __m256i __A, __m256i __B)

VPMAXSB ymm {k}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm256_maskz_max_epi8 __m256i _mm256_maskz_max_epi8(__mmask32 __M, __m256i __A, __m256i __B)

VPMAXSB ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl -mavx512bw

_mm512_max_epi8 __m512i _mm512_max_epi8(__m512i __A, __m512i __B)

VPMAXSB zmm, zmm, zmm EVEX.512 -mavx512bw

_mm512_mask_max_epi8 __m512i _mm512_mask_max_epi8(__m512i __W, __mmask64 __M, __m512i __A, __m512i __B)

VPMAXSB zmm {k}, zmm, zmm EVEX.512 -mavx512bw

_mm512_maskz_max_epi8 __m512i _mm512_maskz_max_epi8(__mmask64 __M, __m512i __A, __m512i __B)

VPMAXSB zmm {k}{z}, zmm, zmm EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512BW_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512BW_256
Same as AVX512BW_128Same as AVX512BW_128
AVX512BW_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512BW
CPUID.(EAX=07H,ECX=0):EBX[30] AVX512BW

Same as AVX512BW_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-316 (PMAXSB/PMAXSW/PMAXSD/PMAXSQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.