x86-64.net

Instruction

VPMAXSD

Returns the larger of each pair of signed doublewords.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMAXSD keeps the larger of each pair of doublewords, compared as signed integers. It is the VEX and EVEX form of SSE4.1’s PMAXSD: VEX.128 needs AVX, VEX.256 AVX2, and the EVEX forms add masking, a broadcast operand and the 512-bit width. Its partners are VPMINSD for the minimum and VPMAXUD for unsigned doublewords, and AVX-512 brought the quadword version VPMAXSQ, which AVX2 lacks.

Signed or unsigned

The two give different answers once a sign bit is set. In cases recorded on Zen 5, the larger of 80000000h and FFFFFFFFh was FFFFFFFFh, -1 being greater than -2147483648, and the larger of 80000000h and 7FFFFFFFh was 7FFFFFFFh, where VPMAXUD would choose 80000000h. Picking the wrong one is a silent bug, so the C type decides: int32_t compiles to VPMAXSD and uint32_t to VPMAXUD.

In compiled code

GCC 14 and Clang 23 at -O2 use it wherever a vectorized loop takes a maximum:

  • Reductions. The largest element of an int32_t array becomes VPMAXSD against memory in the loop, then a few more VPMAXSDs on shuffled halves at the end. Clang keeps four accumulators, so that four independent chains run side by side; GCC keeps one.
  • Clamping. x < lo ? lo : x > hi ? hi : x becomes VPMAXSD with lo followed by VPMINSD with hi, and a clamp at zero before a saturating narrowing store is a VPMAXSD against zero (see VPMOVDB).

For the SSE2 baseline there is no doubleword maximum: both compilers compare with PCMPGTD and combine the two inputs with PAND, PANDN and POR, four instructions instead of one. SSE2’s own maximums, PMAXSW for signed words and PMAXUB for unsigned bytes, cover only those two types; SSE4.1 filled in the rest.

There is no floating-point subtlety here, unlike MAXPS: equal values and the order of the operands make no difference to the result. AMD’s Zen 5 guide lists VPMAXSD as one macro-op with a latency of one cycle, on any of the four vector pipelines.

Forms

Every encoding of VPMAXSD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMAXSD xmm, xmm, m128 VPMAXSD_XMMdq_XMMdq_MEMdqVEX.128.66.0F38.WIG 3D /rAVX
VPMAXSD xmm, xmm, xmm VPMAXSD_XMMdq_XMMdq_XMMdqVEX.128.66.0F38.WIG 3D /rAVX
VPMAXSD ymm, ymm, m256 VPMAXSD_YMMqq_YMMqq_MEMqqVEX.256.66.0F38.WIG 3D /rAVX2
VPMAXSD ymm, ymm, ymm VPMAXSD_YMMqq_YMMqq_YMMqqVEX.256.66.0F38.WIG 3D /rAVX2
VPMAXSD zmm {k}{z}, zmm, zmm VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512EVEX.512.66.0F38.W0 3D /rAVX10.1 or AVX512F
VPMAXSD zmm {k}{z}, zmm, m512/m32bcst VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512EVEX.512.66.0F38.W0 3D /rAVX10.1 or AVX512F
VPMAXSD xmm {k}{z}, xmm, xmm VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512EVEX.128.66.0F38.W0 3D /rAVX10.1 or AVX512F + AVX512VL
VPMAXSD xmm {k}{z}, xmm, m128/m32bcst VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512EVEX.128.66.0F38.W0 3D /rAVX10.1 or AVX512F + AVX512VL
VPMAXSD ymm {k}{z}, ymm, ymm VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512EVEX.256.66.0F38.W0 3D /rAVX10.1 or AVX512F + AVX512VL
VPMAXSD ymm {k}{z}, ymm, m256/m32bcst VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512EVEX.256.66.0F38.W0 3D /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm, m128
xmm {k}{z}, xmm, m128/m32bcst		xmm, xmm, xmm
xmm {k}{z}, xmm, xmm
ymm {k}{z}, ymm, ymm		ymm, ymm, m256
ymm {k}{z}, ymm, m256/m32bcst		ymm, ymm, ymmzmm {k}{z}, zmm, zmmzmm {k}{z}, zmm, m512/m32bcst
Sandy Bridge7 / 0.5p151 / 0.5p15
Haswell7 / 0.5p151 / 0.5p158 / 0.5p151 / 0.5p15
Broadwell6 / 0.5p151 / 0.5p157 / 0.5p151 / 0.5p15
Skylake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p01
Skylake-SP, Ice Lake7 / 0.5p011 / 0.5p018 / 0.5p011 / 0.5p011 / 1p08 / 1p0
Alder Lake8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p01
Sapphire Rapids8 / 0.5p011 / 0.5p019 / 0.5p011 / 0.5p011 / 1p09 / 1p0
Lunar Lake7 / 2V0 V11 / 0.5V0 V18 / 2.33V0 V11 / 0.5V0 V1
Piledriver7 / 1.5FPMAL2 / 0.5FPMAL FPU2 FPU3
Zen8 / 0.5FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.67FPU0 FPU1 FPU31 / 0.67FPU0 FPU1 FPU3
Zen 28 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU38 / 0.33FPU0 FPU1 FPU31 / 0.33FPU0 FPU1 FPU3
Zen 38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP3
Zen 48 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP31 / 0.25FP0 FP1 FP2 FP31 / 0.5FP0 FP1 FP2 FP38 / 0.5FP0 FP1 FP2 FP3
Jaguar6 / 1FPU0 FPU1 VALU0 VALU11 / 0.5FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Element-wise: each doubleword of the result comes from the doubleword in the same place in each source.
VPMAXSD: element by elementResult doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.0123xmm2a1110k1r0r1r3xmm10123xmm3or m128b

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}. With m32bcst, one doubleword from memory stands for every element of the last source.

Result doubleword i comes from doubleword i of xmm2 and xmm3. Result doublewords 3 to 0: r3, unchanged (bit 2 of k1 is 0), r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:  # 1 without a write mask
        sa = zmm2.sd[i]
        sb = src3.sd[i]
        zmm1.d[i] = max(sa, sb)
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# m32bcst: src3.d[i] is the m32 for every i
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMAXSD xmm, xmm, xmm/m128 VPMAXSD ymm, ymm, ymm/m256
xmm, ymmexplicitwrite
xmm, ymmexplicitread
xmm/m128, ymm/m256explicitread
VPMAXSD xmm {k}{z}, xmm, xmm/m128/m32bcst VPMAXSD ymm {k}{z}, ymm, ymm/m256/m32bcst VPMAXSD zmm {k}{z}, zmm, zmm/m512/m32bcst
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm, ymm, zmmexplicitread
xmm/m128/m32bcst, ymm/m256/m32bcst, zmm/m512/m32bcstexplicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-4
EVEX forms
AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMAXSD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_max_epi32 __m128i _mm_max_epi32(__m128i __V1, __m128i __V2)

VPMAXSD xmm, xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_max_epi32 __m128i _mm_mask_max_epi32(__m128i __W, __mmask8 __M, __m128i __A, __m128i __B)

VPMAXSD xmm {k}, xmm, xmm EVEX.128 -mavx512vl

_mm_maskz_max_epi32 __m128i _mm_maskz_max_epi32(__mmask8 __M, __m128i __A, __m128i __B)

VPMAXSD xmm {k}{z}, xmm, xmm EVEX.128 -mavx512vl

_mm256_max_epi32 __m256i _mm256_max_epi32(__m256i __a, __m256i __b)

VPMAXSD ymm, ymm, ymm VEX.256 -mavx2

_mm256_mask_max_epi32 __m256i _mm256_mask_max_epi32(__m256i __W, __mmask8 __M, __m256i __A, __m256i __B)

VPMAXSD ymm {k}, ymm, ymm EVEX.256 -mavx512vl

_mm256_maskz_max_epi32 __m256i _mm256_maskz_max_epi32(__mmask8 __M, __m256i __A, __m256i __B)

VPMAXSD ymm {k}{z}, ymm, ymm EVEX.256 -mavx512vl

_mm512_max_epi32 __m512i _mm512_max_epi32(__m512i __A, __m512i __B)

VPMAXSD zmm, zmm, zmm EVEX.512 -mavx512f

_mm512_mask_max_epi32 __m512i _mm512_mask_max_epi32(__m512i __W, __mmask16 __M, __m512i __A, __m512i __B)

VPMAXSD zmm {k}, zmm, zmm EVEX.512 -mavx512f

_mm512_maskz_max_epi32 __m512i _mm512_maskz_max_epi32(__mmask16 __M, __m512i __A, __m512i __B)

VPMAXSD zmm {k}{z}, zmm, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-316 (PMAXSB/PMAXSW/PMAXSD/PMAXSQ)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.