VPMAXSQ

VPMAXSQ keeps the larger of each pair of quadwords, compared as signed integers. VPMAXSD explains why the C type chooses between the signed and the unsigned form and where compiled code takes maximums, in reductions and clamps; VPMAXSQ brings that to int64_t, which SSE and AVX2 never covered. It is AVX-512F, in EVEX encodings only, with masking, a broadcast operand and the 512-bit width; VPMINSQ is the minimum and VPMAXUQ the unsigned maximum. In the cases recorded on Zen 5, the larger of 8000000000000000h and FFFFFFFFFFFFFFFFh was all ones, -1, and a broadcast 0 replaced -1 but not 7FFFFFFFFFFFFFFFh: the clamp at zero in one instruction.

Without it#

With -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile a[i] > b[i] ? a[i] : b[i] over int64_t to a VPCMPGTQ and a blend by the compare’s result, VPBLENDVB in GCC and VBLENDVPD in Clang. The largest element of an array takes the same pair of instructions per vector in the loop and at each halving step at the end. With -march=x86-64-v4 both become VPMAXSQ, against memory in the loop; Clang keeps four YMM accumulators and GCC one ZMM, which it narrows with VEXTRACTI64X4 and VEXTRACTI64X2 before the last VPMAXSQs. Signed saturation from 64 to 32 bits, where GCC clamps with VPMAXSQ and VPMINSQ before permuting, is on the VPMOVQD page.

On Zen 5#

The quadword form is slower than the doubleword one. AMD’s latency spreadsheet for Zen 5 lists VPMAXSQ as one macro-op with a latency of 2 cycles on the pipes FP0 and FP3, the same as VPMINSQ, VPMINUQ and VPABSQ, where VPMAXSD takes one cycle on any of the four vector pipes.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        sa = zmm2.sq[i]
        sb = src3.sq[i]
        zmm1.q[i] = max(sa, sb)
    elif zeroing:
        zmm1.q[i] = 0
    # else: zmm1.q[i] keeps its value
# m64bcst: src3.q[i] is the m64 for every i
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

embedded broadcast (tuple Full); memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMAXSQ, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q

All 686 AVX10.1 instructions