VPMAXSW

VPMAXSW keeps the larger of each pair of words, compared as signed 16-bit integers: the VEX and EVEX form of SSE2’s PMAXSW, whose page covers ReLU, reductions and the baseline’s detour for unsigned words, which VPMAXUW now does in one step. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and add a write mask per word, but no broadcast. Every form writes a separate destination, zeroes it above the vector length and reads memory at any alignment. On Zen 5, vpmaxsw ymm12, ymm6, ymmword ptr [mem] kept 7FFFh over 0001h, 0001h over 8000h and 0001h over FFFFh, 1 over -1, and {evex} vpmaxsw xmm17, xmm30, xmm2 kept 7FFFh over 8000h, where VPMAXUW keeps 8000h.

In compiled code#

In our builds at -O2 over fixed-size int16_t arrays, b[i] > c[i] ? b[i] : c[i] is one VPMAXSW per vector with its second operand in memory in GCC 14 and Clang 23, and b[i] > 0 ? b[i] : 0 the same against a zeroed register, with -march=x86-64-v3 and -march=x86-64-v4; GCC moves to zmm registers at -v4.

• The largest element. GCC folds the array into one register with VPMAXSW and halves it, with VEXTRACTI128 at -v3 or VEXTRACTI64X4 and VEXTRACTI32X4 at -v4, then VPSRLDQ by 8, 4 and 2, and reads word 0 with VPEXTRW. Clang stops at 128 bits, XORs every word with 7FFFh, which turns the signed maximum into an unsigned minimum, lets VPHMINPOSUW find it and XORs the result back.
• A condition. if (c[i] & 1) a[i] = max(b[i], a[i]) stays scalar with CMOVL in GCC at -v3, and Clang stores word by word with VPEXTRW; at -v4 both compute VPMAXSW for every word and store under a word mask with VMOVDQU16.

VPMINSW is its partner. AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle, four per cycle on pipes FP0 to FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        sa = zmm2.sw[i]
        sb = src3.sw[i]
        zmm1.w[i] = max(sa, sb)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMAXSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPERMILPS
• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ

All 253 AVX instructions

More AVX2 instructions

• VPERMD
• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W

All 686 AVX10.1 instructions