VPMAXUB

VPMAXUB keeps the larger of each pair of bytes, compared as unsigned numbers: the VEX and EVEX form of PMAXUB, whose page covers the operation and its uses in baseline code. The newer encodings write a separate destination, read memory at any alignment and zero the register above the vector length. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1, take a mask bit per byte and cannot broadcast. On Zen 5, vpmaxub xmm1, xmm2, xmm3 chose 80h over 00h, where the signed VPMAXSB keeps 00h, FFh over 01h and 80h over 01h, and vpmaxub ymm7{k6}{z}, ymm12, ymm7 wrote maxima into the bytes k6 selects and zeroed the rest.

In compiled code#

In our builds at -O2 over fixed-size uint8_t arrays, the plain maximum is one VPMAXUB per vector in GCC 14 and Clang 23, on ymm registers at -march=x86-64-v3, and on zmm registers in GCC at -v4.

• A range. Clamping to 16..235, x < 16 ? 16 : x > 235 ? 235 : x, is VPMAXUB with 16 and VPMINUB with 235, both constants broadcast once before the loop.
• A condition. if (m[i]) a[i] = max(b[i], c[i]) stays a scalar loop with CMOVB in GCC at -v3, and Clang stores byte by byte with VPEXTRB under branches. At -v4 both compute VPMAXUB over every byte and store under a byte mask with VMOVDQU8, Clang making the mask with VPTESTMB, GCC with VPCMPNEQB against zero, followed by a KORTESTQ that skips blocks with no byte set.
• The largest byte. Both fold the array into one register with VPMAXUB. GCC then halves it with VEXTRACTI128, or VEXTRACTI64X4 and VEXTRACTI32X4 at -v4, and VPSRLDQ by 8, 4, 2 and 1; Clang inverts the bytes and finishes with VPHMINPOSUW, as on PMAXUB’s page.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle and four per cycle on any of pipes FP0 to FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        a = zmm2.b[i]
        b = src3.b[i]
        zmm1.b[i] = max(a, b)
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMAXUB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPEXTRB
• VPEXTRD
• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD

All 253 AVX instructions

More AVX2 instructions

• VPERMPD
• VPERMPS
• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPEXTRQ
• VPEXTRW
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M

All 686 AVX10.1 instructions