VPMAXUW

VPMAXUW keeps the larger of each pair of words, compared as unsigned numbers: the VEX and EVEX form of SSE4.1’s PMAXUW, whose page shows the baseline code that stands in for it. The newer encodings write a separate destination, read memory at any alignment and zero the register above the vector length. VEX.128 needs AVX and VEX.256 AVX2; the EVEX forms need AVX512BW (with AVX512VL below 512 bits) or AVX10.1 and add a write mask per word, but no broadcast form. On Zen 5, vpmaxuw xmm1, xmm2, xmmword ptr [mem] kept 8000h over 0000h, where the signed VPMAXSW keeps 0000h, and FFFFh over 8000h; vpmaxuw zmm14{k4}, zmm8, zmmword ptr [mem] wrote maximums only into the words k4 selects and left the others as they were.

In compiled code#

In our builds at -O2 over fixed-size uint16_t arrays, the plain maximum is one VPMAXUW per vector in GCC 14 and Clang 23, on ymm registers at -march=x86-64-v3, and on zmm registers in GCC at -v4.

• A range. b[i] > 1000 ? 1000 : b[i] < 10 ? 10 : b[i] is VPMAXUW with 10 and VPMINUW with 1000, both constants broadcast once before the loop.
• Absolute differences. Clang computes b[i] > c[i] ? b[i] - c[i] : c[i] - b[i] as the maximum minus the minimum, VPMAXUW, VPMINUW and VPSUBW, at both levels. GCC subtracts both ways and selects with VPSUBUSW, VPCMPEQW and VPBLENDVB at -v3, and under a mask from VPCMPNLEUW at -v4.
• A condition. For if (c[i] & 1) a[i] = max(b[i], a[i]) at -v4, both compute VPMAXUW for every word and store under a word mask with VMOVDQU16, rather than masking the maximum itself.
• A reduction. Clang ends the maximum of an array with VPHMINPOSUW over inverted words, as PHMINPOSUW’s page describes; GCC folds the last vector with VPMAXUW and byte shifts.

AMD’s latency spreadsheet for Zen 5 gives its VEX and EVEX rows alike one cycle and four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        a = zmm2.w[i]
        b = src3.w[i]
        zmm1.w[i] = max(a, b)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMAXUW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPEXTRQ
• VPEXTRW
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ

All 253 AVX instructions

More AVX2 instructions

• VPERMQ
• VPGATHERDD
• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ

All 138 AVX2 instructions

More AVX10.1 instructions

• VPGATHERDQ
• VPGATHERQD
• VPGATHERQQ
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW

All 686 AVX10.1 instructions