VPMINSW

VPMINSW keeps the smaller of each pair of words, compared as signed 16-bit integers: the VEX and EVEX form of SSE2’s PMINSW, whose page covers clamping, reductions and absolute values. VPMAXSW, its partner, gives what the newer encodings add: a separate destination, memory at any alignment, zeroing above the vector length, AVX2 for the ymm form, and AVX512BW or AVX10.1 for the EVEX forms with a write mask per word. On Zen 5, vpminsw xmm0, xmm13, xmm9 kept FFFFh over 0001h, 8000h over 0001h and 0001h over 7FFFh, and vpminsw xmm9{k4}{z}, xmm9, xmmword ptr [mem] wrote the five words K4 selects and zeroed word 4, whose minimum would have been 0001h.

Clamping and narrowing#

In our builds at -O2 over fixed-size int16_t arrays, b[i] < c[i] ? b[i] : c[i] is one VPMINSW per vector in GCC 14 and Clang 23, and clamping to -100..100 a VPMAXSW and a VPMINSW against broadcast constants, with -march=x86-64-v3 and -march=x86-64-v4. Narrowing shows the compilers apart:

• To uint8_t. For b[i] > 255 ? 255 : b[i] < 0 ? 0 : b[i], GCC clamps with VPMAXSW and VPMINSW, clears the high bytes with VPAND and packs with VPACKUSWB and VPERMQ at -v3, or narrows with VPMOVWB at -v4. Clang sees that VPACKUSWB saturates by itself and uses it alone at -v3; at -v4 it keeps only the VPMAXSW with zero, since VPMOVUSWB reads the words as unsigned.
• To int8_t. Clamping to -128..127 is VPMAXSW and VPMINSW in GCC, and no minimum at all in Clang, which packs with VPACKSSWB or narrows with VPMOVSWB.
• Absolute differences. For b[i] > c[i] ? b[i] - c[i] : c[i] - b[i], Clang subtracts the minimum from the maximum, VPMINSW, VPMAXSW and VPSUBW, at both levels. GCC subtracts both ways and selects, with VPCMPGTW and VPBLENDVB at -v3, and at -v4 with VPCMPNLEW and a VPSUBW merged under its mask.

AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle, four per cycle on pipes FP0 to FP3.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:  # 1 without a write mask
        sa = zmm2.sw[i]
        sb = src3.sw[i]
        zmm1.w[i] = min(sa, sb)
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMINSW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPHADDSW
• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW

All 253 AVX instructions

More AVX2 instructions

• VPGATHERQD
• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW

All 138 AVX2 instructions

More AVX10.1 instructions

• VPINSRD
• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD

All 686 AVX10.1 instructions