VPMINUB

VPMINUB keeps the smaller of each pair of bytes, compared as unsigned numbers: the VEX and EVEX form of PMINUB, whose page covers the operation and the unsigned comparisons built from it. VPMAXUB, its partner, gives what the newer encodings add (a separate destination, memory at any alignment, zeroing above the vector length, AVX2 for the ymm form, AVX512BW or AVX10.1 for the EVEX forms with a write mask per byte) and the range clamp built from the pair. On Zen 5, vpminub xmm7, xmm11, xmm7 kept 01h over FFh and over 80h, and 7Fh over 80h, where the signed VPMINSB keeps 80h as -128.

Unsigned compares#

AVX2 orders bytes only as signed numbers. In our builds at -O2 over fixed-size uint8_t arrays with -march=x86-64-v3, b[i] <= c[i] ? 0xFF : 0 is VPMINUB and VPCMPEQB in GCC 14 and Clang 23. For b[i] > c[i], Clang inverts that result with VPXOR against all ones, while GCC tests a saturating difference, VPSUBUSB, for zero. Clang also tests the range of a lowercase conversion, (uint8_t)(b[i] - 'A') < 26, with VPMINUB and VPCMPEQB, and it computes absolute differences as VPMAXUB minus VPMINUB at both levels.

With -march=x86-64-v4 the compares move to mask registers: VPCMPUB, as VPCMPLEUB or VPCMPNLEUB, then VPMOVM2B to expand the mask into bytes in Clang, or a zero-masked VMOVDQU8 of all ones in GCC. In the conversion, Clang’s VPCMPLTUB mask selects the bytes to change with a masked VMOVDQU8, and GCC’s VPCMPLEUB mask adds 20h to them with a masked VPADDB.

The minimum of a whole array ends in VPHMINPOSUW in Clang, after VPSRLW and VPMINUB fold each pair of bytes into a word, with no inversion needed; GCC halves the register with VPSRLDQ and VPMINUB. AMD’s latency spreadsheet for Zen 5 gives the VEX and EVEX rows alike one cycle and four per cycle.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    if k1[i]:  # 1 without a write mask
        a = zmm2.b[i]
        b = src3.b[i]
        zmm1.b[i] = min(a, b)
    elif zeroing:
        zmm1.b[i] = 0
    # else: zmm1.b[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-4

EVEX forms

AVX512-E4

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMINUB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPHADDW
• VPHMINPOSUW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPINSRB
• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD

All 253 AVX instructions

More AVX2 instructions

• VPGATHERQQ
• VPHADDD
• VPHADDSW
• VPHADDW
• VPHSUBD
• VPHSUBSW
• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPINSRQ
• VPINSRW
• VPLZCNTD
• VPLZCNTQ
• VPMADD52HUQ
• VPMADD52LUQ
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW

All 686 AVX10.1 instructions