VPMOVB2M instruction (AVX10.1)

VPMOVB2M copies the top bit of every byte of a vector into a mask register: bit i of the destination is bit 7 of byte i, 16, 32 or 64 bits for the xmm, ymm and zmm forms, and the mask bits above are cleared. It is AVX-512’s counterpart of PMOVMSKB, whose page covers the uses of such a bit set, but its result lands in a mask register, where it can drive a masked instruction directly, and the zmm form gives all 64 bits. A case recorded on Zen 5 with the xmm form wrote 420Bh, clearing the 48 bits above that the register had held. VPMOVW2M takes the top bit of words, and VPMOVD2M and VPMOVQ2M, from AVX512DQ, those of doublewords and quadwords.

A test for negative bytes

The top bit is the sign of a signed byte, so VPMOVB2M is a compare with zero, a < 0, that needs no zeroed register. Clang 23 at -O2 with -march=x86-64-v4 uses it that way: _mm512_cmplt_epi8_mask(a, zero) becomes one VPMOVB2M, while GCC 14 zeroes a register and emits VPCMPB with predicate 1. For the intrinsic _mm512_movepi8_mask both emit VPMOVB2M, followed by KMOVQ when the mask goes to a general-purpose register. Neither turned a loop that collects the sign bits of 64 bytes one by one into it.

Blending by sign

A byte whose top bit says which of two values to take is how PBLENDVB reads its third operand. AVX-512 blends under a mask instead, so code ported from SSE or AVX2 turns such a selector into a mask first: _mm512_mask_blend_epi8(_mm512_movepi8_mask(sel), x, y) compiles, in both compilers, to VPMOVB2M and a VPBLENDMB. VPMOVM2B goes the other way.

AMD’s Zen 5 guide lists VPMOVB2M with the latencies of the compares into a mask, 3, 4 and 6 cycles for xmm, ymm and zmm.

Forms

Every encoding of VPMOVB2M that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVB2M k, xmm` VPMOVB2M_MASKmskw_XMMu8_AVX512	`EVEX.128.F3.0F38.W0 29 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVB2M k, ymm` VPMOVB2M_MASKmskw_YMMu8_AVX512	`EVEX.256.F3.0F38.W0 29 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVB2M k, zmm` VPMOVB2M_MASKmskw_ZMMu8_AVX512	`EVEX.512.F3.0F38.W0 29 /r`	AVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, xmm` `k, ymm` `k, zmm`
Skylake-SP, Ice Lake	1 / 1p0
Sapphire Rapids	3 / 1p0
Zen 4	1 / 1¹ALU0 ALU1 ALU2 ALU3

Zen 4 model, xmm form: AMD's spreadsheets give latency 3 for Zen 4 and Zen 5 (AMD 57647, row 2523; AMD 58455, row 756).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each byte of the source sets one bit of k1, bit i for byte i.

Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms.

Bit i of k1 comes from byte i of xmm2. Result bits 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    k1[i] = zmm2.sb[i] < 0
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVB2M k, xmm` `VPMOVB2M k, ymm` `VPMOVB2M k, zmm`
`k`	explicit	write
`xmm, ymm, zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVB2M, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_movepi8_mask` `__mmask64 _mm512_movepi8_mask(__m512i __A)`	`VPMOVB2M k, zmm` EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512BW_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512BW_256` AVX10.1	Same as `AVX512BW_128`	Same as `AVX512BW_128`
`AVX512BW_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Same as `AVX512BW_128`

AVX512BW_128