VPMOVD2M instruction (AVX10.1)

VPMOVD2M copies the top bit of every doubleword of a vector into a mask register: bit i of the destination is bit 31 of doubleword i, 4, 8 or 16 bits for the XMM, YMM and ZMM forms, and the mask bits above are cleared. It is the doubleword form of VPMOVB2M, whose page explains the uses, and of VPMOVW2M; VPMOVM2D goes the other way. It came with AVX512DQ. With singles, the bit is the sign, the same bit that VMOVMSKPS moves to a general-purpose register.

Recorded on Zen 5

Only the sign bit. {evex} vpmovd2m k2, ymm9 read 80000000h at elements 0 and 6 and 7FFFFFFFh, 0, 0Fh, 10h and 8 elsewhere, and wrote 41h; K2 lost all its other bits.
ZMM. vpmovd2m k1, zmm7 gave A105h, bits 0, 2, 8, 13 and 15, for 80000000h three times and FFFFFFFFh twice.
Nothing negative. From 0, 0Fh, 10h and 8, vpmovd2m k4, xmm17 wrote 0 to all 64 bits of K4.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 do not use VPMOVD2M for a sign test in a loop: w[i] < 0 ? x[i] : y[i] over int32_t compares with zero, as VPCMPD with predicate 1 in GCC and VPCMPGTD against a zero register in Clang, and counting the negative elements is a compare in GCC and a VPSRLD by 31 in Clang. Only _mm512_movepi32_mask gives VPMOVD2M, followed by KMOVW in GCC and KMOVD in Clang; _mm256_movemask_ps stays VMOVMSKPS.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2 and a latency of 3, 4 and 6 cycles for XMM, YMM and ZMM sources.

Forms

Every encoding of VPMOVD2M that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVD2M k, xmm` VPMOVD2M_MASKmskw_XMMu32_AVX512	`EVEX.128.F3.0F38.W0 39 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVD2M k, ymm` VPMOVD2M_MASKmskw_YMMu32_AVX512	`EVEX.256.F3.0F38.W0 39 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVD2M k, zmm` VPMOVD2M_MASKmskw_ZMMu32_AVX512	`EVEX.512.F3.0F38.W0 39 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, xmm` `k, ymm` `k, zmm`
Skylake-SP, Ice Lake	1 / 1p0
Sapphire Rapids	3 / 1p0
Zen 4	1 / 1ALU0 ALU1 ALU2 ALU3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each doubleword of the source sets one bit of k1, bit i for doubleword i.

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms.

Bit i of k1 comes from doubleword i of xmm2. Result bits 3 to 0: r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    k1[i] = zmm2.sd[i] < 0
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVD2M k, xmm` `VPMOVD2M k, ymm` `VPMOVD2M k, zmm`
`k`	explicit	write
`xmm, ymm, zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVD2M, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_movepi32_mask` `__mmask16 _mm512_movepi32_mask(__m512i __A)`	`VPMOVD2M k, zmm` EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512DQ_256` AVX10.1	Same as `AVX512DQ_128`	Same as `AVX512DQ_128`
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Same as `AVX512DQ_128`

AVX512DQ_128