VPMOVDB

VPMOVDB narrows each doubleword to a byte by keeping its low 8 bits: 16 doublewords of a ZMM register become 16 bytes in an XMM register or in memory, 8 from a YMM register and 4 from an XMM one. The register form zeroes the destination above the bytes it writes. It is the reverse of VPMOVZXBD and VPMOVSXBD, and one of AVX-512F’s family of down conversions, from VPMOVQB to VPMOVWB.

Straight to memory#

The memory form is a narrowing store: no register holds the 16 bytes first. Under a write mask it writes only the bytes whose bits are set and leaves the others in memory alone, without faulting on them, so a loop can store its last few results without running past the end of the buffer. For d[i] = (uint8_t)a[i] over uint32_t arrays, Clang 23 at -O2 with -march=x86-64-v4 loads 8 doublewords at a time and stores each 8 bytes with vpmovdb qword ptr [rdi + rdx], ymm0; GCC 14 keeps that loop scalar at -O2. With only AVX2, Clang needs a VPSHUFB per 16 bytes of input to gather the low bytes, then unpacks and a VPERMQ to bring the pieces together. The intrinsics _mm512_cvtepi32_epi8 and _mm512_mask_cvtepi32_storeu_epi8 compile to the register and masked memory forms in both compilers.

Truncation or saturation#

VPMOVDB wraps: 300 becomes 44 and -1 becomes 255. Its siblings saturate instead: VPMOVSDB clamps signed values to -128 to 127, and VPMOVUSDB clamps to 0 to 255, but takes the source as unsigned, so a negative doubleword becomes 255, not 0. Clang therefore vectorizes d[i] = x < 0 ? 0 : x > 255 ? 255 : x as VPMAXSD against zero followed by VPMOVUSDB. The SSE packs, PACKUSDW and PACKUSWB, saturate signed inputs to unsigned in one step, but halve the width only once and interleave two sources lane by lane.

AMD’s Zen 5 guide lists the ZMM register form as one macro-op with a latency of 5 cycles, and the memory form as two.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        xmm1.b[i] = zmm2.d[i]  # the low bits
    elif zeroing:
        xmm1.b[i] = 0
    # else: xmm1.b[i] keeps its value
for i in range(VL // 32, 16):
    xmm1.b[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 32):
    if k1[i]:
        mem.b[i] = zmm2.d[i]  # the low bits
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVDB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD

All 686 AVX10.1 instructions