VPMOVDW

VPMOVDW narrows each doubleword to a word by keeping its low 16 bits: 16 doublewords of a ZMM register become 16 words in a YMM register or in memory, 8 from a YMM register and 4 from an XMM one. It is the word form of VPMOVDB, whose page explains the narrowing store and the saturating siblings, here VPMOVSDW and VPMOVUSDW, and the reverse of VPMOVZXWD and VPMOVSXWD.

Recorded on Zen 5#

• Truncation. {evex} vpmovdw xmm1, xmm2 turned 00000001h, FFFFFFFFh, 00007FFFh and 00008000h into 0001h, FFFFh, 7FFFh and 8000h; elsewhere 00010000h gave 0000h and 7FFFFFFFh FFFFh. The register form cleared XMM1 above its 64 bits of result.
• Masked store. vpmovdw qword ptr [mem]{k5}, xmm17, with only bit 0 of the four that count set in K5, wrote 8000h, the low word of FFFF8000h, and left the other three words of memory as they were.
• Zeroing. vpmovdw xmm14{k5}{z}, ymm8 wrote words 0, 5, 6 and 7 from FFFFFFFFh, FFFF7FFFh, 0000FFFFh and 00010000h, giving FFFFh, 7FFFh, FFFFh and 0000h, and zeroed the other four.

In compiled code#

For d[i] = (uint16_t)a[i] over uint32_t arrays, Clang 23 at -O2 with -march=x86-64-v4 loads 8 doublewords at a time and stores 8 words with vpmovdw xmmword ptr [...], ymm0, also in a loop of unknown length. GCC 14 instead joins the low words of two ZMM loads with one VPERMT2W and a table of indices, and leaves the loop of unknown length scalar. Clamping to int16_t first, Clang uses VPMOVSDW, GCC VPMINSD, VPMAXSD and the same VPERMT2W. Both compile _mm512_cvtepi32_epi16 and _mm512_mask_cvtepi32_storeu_epi16 to the register and masked memory forms.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2 cycles from an XMM source and 4 from a YMM or ZMM one, and the memory forms two macro-ops, 5 cycles from a YMM or ZMM register.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        ymm1.w[i] = zmm2.d[i]  # the low bits
    elif zeroing:
        ymm1.w[i] = 0
    # else: ymm1.w[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

for i in range(VL // 32):
    if k1[i]:
        mem.w[i] = zmm2.d[i]  # the low bits
    # else: mem.w[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSQ
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ

All 686 AVX10.1 instructions