VPMOVM2B instruction (AVX10.1)

VPMOVM2B turns a mask register into a vector: byte i of the destination becomes FFh where bit i of the mask is 1 and 00h where it is 0, for 16, 32 or 64 bytes. It takes no write mask, and the bits of the register above the vector length are cleared. In a case recorded on Zen 5, the xmm form with a mask whose low byte was A5h wrote FFh to bytes 0, 2, 5 and 7. VPMOVM2W does the same for words, and VPMOVM2D and VPMOVM2Q, from AVX512DQ, for doublewords and quadwords; VPMOVB2M is the reverse.

Compares that return vectors

The compares of SSE and AVX, such as PCMPEQB, write a vector of FFh and 00h bytes; AVX-512’s write a mask, and the EVEX encoding of VPCMPEQB has no vector result. So where C asks for a vector, VPMOVM2B rebuilds one. For a == b on 64-byte vectors of char, GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 emit a compare into k0 and VPMOVM2B; for 32-byte vectors they use the VEX VPCMPEQB, which writes the vector directly. For a < 0, Clang takes the mask from the sign bits with VPMOVB2M and GCC from a VPCMPB, and both finish with VPMOVM2B.

The same instruction expands any bit set into bytes, for example a 64-bit value moved in with KMOVQ from a bitmap, so that byte-wise instructions without masking, such as VPSHUFB or a store of the vector, can use it. The intrinsic is _mm512_movm_epi8.

AMD’s Zen 5 guide lists VPMOVM2B as one macro-op with a latency of 1 cycle that runs on any of four pipes, where the compares into a mask take 3 to 6 cycles on two.

Forms

Every encoding of VPMOVM2B that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVM2B xmm, k` VPMOVM2B_XMMu8_MASKmskw_AVX512	`EVEX.128.F3.0F38.W0 28 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVM2B ymm, k` VPMOVM2B_YMMu8_MASKmskw_AVX512	`EVEX.256.F3.0F38.W0 28 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVM2B zmm, k` VPMOVM2B_ZMMu8_MASKmskw_AVX512	`EVEX.512.F3.0F38.W0 28 /r`	AVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, k` `ymm, k`	`zmm, k`
Skylake-SP, Ice Lake	1 / 0.33p015	1 / 0.5p05
Sapphire Rapids	3 / 0.33p015	3 / 0.5p05
Zen 4	0 / 0.17¹	0 / 0.17²

Zen 4 model: AMD's spreadsheets give latency 1 for Zen 4 and Zen 5 (AMD 57647, row 2541; AMD 58455, row 752).
Zen 4 model: AMD's spreadsheets give latency 1 for Zen 4 and Zen 5 (AMD 57647, row 2543; AMD 58455, row 752).

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

From a mask: each bit of k2 becomes a whole byte, all ones for 1 and zero for 0.

Shown: bytes 7 to 0. Every byte works alike: 16, 32 and 64 bytes in the xmm, ymm and zmm forms.

Result byte i comes from bit i of k2. Result bytes 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 8):
    zmm1.b[i] = -1 if k2[i] else 0  # all ones or zero
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVM2B xmm, k` `VPMOVM2B ymm, k` `VPMOVM2B zmm, k`
`xmm, ymm, zmm`	explicit	write
`k`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVM2B, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movm_epi8` `__m128i _mm_movm_epi8(__mmask16 __A)`	`VPMOVM2B xmm, k` EVEX.128 -mavx512vl -mavx512bw
`_mm256_movm_epi8` `__m256i _mm256_movm_epi8(__mmask32 __A)`	`VPMOVM2B ymm, k` EVEX.256 -mavx512vl -mavx512bw
`_mm512_movm_epi8` `__m512i _mm512_movm_epi8(__mmask64 __A)`	`VPMOVM2B zmm, k` EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512BW_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512BW_256` AVX10.1	Same as `AVX512BW_128`	Same as `AVX512BW_128`
`AVX512BW_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Same as `AVX512BW_128`

AVX512BW_128