VPMOVM2D instruction (AVX10.1)

VPMOVM2D turns a mask register into a vector of doublewords: element i becomes FFFFFFFFh where bit i of the mask is 1 and 0 where it is 0, for 4, 8 or 16 elements. It is the doubleword form of VPMOVM2B, whose page explains why AVX-512 code needs it: its compares write masks, where C and the older compares such as VPCMPGTD want vectors. Unlike the byte and word forms it belongs to AVX512DQ, with VPMOVM2Q; VPMOVD2M goes the other way.

Recorded on Zen 5

The three cases set exactly the elements of the mask’s low bits and cleared everything above the vector length:

vpmovm2d xmm1, k1, with 3h in the low nibble of K1, wrote FFFFFFFFh to elements 0 and 1 and cleared the rest of ZMM1.
vpmovm2d ymm24, k4, low byte 0Ah, set elements 1 and 3.
vpmovm2d zmm14, k6, low word EC3Ah, set the nine elements of its set bits and read none of bits 63:16.

In compiled code

For a < b on 64-byte vector types of int, GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compare into a mask, GCC with VPCMPD and Clang with the EVEX VPCMPGTD with swapped operands, and VPMOVM2D builds the vector of -1 and 0. On 32-byte vectors both use the VEX VPCMPGTD, which writes the vector directly. In a loop storing -(a[i] < b[i]) over int arrays GCC writes all ones under the compare mask instead, with a zero-masked VMOVDQA32 of a register filled by VPTERNLOGD, and Clang stays with the VEX compare on YMM registers. _mm512_movm_epi32 is VPMOVM2D in both.

AMD’s Zen 5 latency spreadsheet lists VPMOVM2D as one macro-op with a latency of one cycle on any of the four pipes FP0 to FP3, four per cycle.

Forms

Every encoding of VPMOVM2D that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVM2D xmm, k` VPMOVM2D_XMMu32_MASKmskw_AVX512	`EVEX.128.F3.0F38.W0 38 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVM2D ymm, k` VPMOVM2D_YMMu32_MASKmskw_AVX512	`EVEX.256.F3.0F38.W0 38 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVM2D zmm, k` VPMOVM2D_ZMMu32_MASKmskw_AVX512	`EVEX.512.F3.0F38.W0 38 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, k` `ymm, k`	`zmm, k`
Skylake-SP, Ice Lake, Sapphire Rapids	1 / 0.33p015	1 / 0.5p05
Zen 4	0 / 0.17	0 / 0.17

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

From a mask: each bit of k2 becomes a whole doubleword, all ones for 1 and zero for 0.

Every doubleword works alike: 4, 8 and 16 doublewords in the xmm, ymm and zmm forms.

Result doubleword i comes from bit i of k2. Result doublewords 3 to 0: a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    zmm1.d[i] = -1 if k2[i] else 0  # all ones or zero
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVM2D xmm, k` `VPMOVM2D ymm, k` `VPMOVM2D zmm, k`
`xmm, ymm, zmm`	explicit	write
`k`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVM2D, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movm_epi32` `__m128i _mm_movm_epi32(__mmask8 __A)`	`VPMOVM2D xmm, k` EVEX.128 -mavx512vl -mavx512dq
`_mm256_movm_epi32` `__m256i _mm256_movm_epi32(__mmask8 __A)`	`VPMOVM2D ymm, k` EVEX.256 -mavx512vl -mavx512dq
`_mm512_movm_epi32` `__m512i _mm512_movm_epi32(__mmask16 __A)`	`VPMOVM2D zmm, k` EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512DQ_256` AVX10.1	Same as `AVX512DQ_128`	Same as `AVX512DQ_128`
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Same as `AVX512DQ_128`

AVX512DQ_128