VPMOVM2Q instruction (AVX10.1)

VPMOVM2Q turns a mask register into a vector of quadwords: element i becomes all ones where bit i of the mask is 1 and 0 where it is 0, for 2, 4 or 8 elements, and the register is cleared above the vector length. It belongs to AVX512DQ with VPMOVM2D, whose page explains its place, and VPMOVM2B why AVX-512 code needs it; VPMOVQ2M goes the other way.

Recorded on Zen 5

Two elements. vpmovm2q xmm24, k1, with the low two bits of K1 clear (0Ch in its low byte), wrote zero to all of ZMM24.
Four. vpmovm2q ymm1, k2, low nibble Ah, set elements 1 and 3.
Eight. vpmovm2q zmm24, k7, low byte C5h, set elements 0, 2, 6 and 7 and read none of bits 63:8.

In compiled code

For a < b on 64-byte vector types of long long, GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compare into K0, GCC with VPCMPQ predicate 1 and Clang with the EVEX VPCMPGTQ with swapped operands, and VPMOVM2Q builds the vector; on 32-byte vectors both use the VEX VPCMPGTQ. The same goes for a compare of two vectors of doubles whose result is a vector of long long: VCMPPD into K0 and VPMOVM2Q in both. In a loop storing -(a[i] < b[i]) over int64_t arrays, Clang stays with the VEX VPCMPGTQ on YMM registers, and GCC selects 1 under each compare mask, packs to doublewords, negates and widens back with VPMOVSXDQ. _mm512_movm_epi64 and _mm_movm_epi64 are VPMOVM2Q after a KMOVB in GCC and a KMOVD in Clang.

AMD’s Zen 5 latency spreadsheet lists VPMOVM2Q as one macro-op with a latency of one cycle on any of the four pipes FP0 to FP3, four per cycle, as VPMOVM2D.

Forms

Every encoding of VPMOVM2Q that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVM2Q xmm, k` VPMOVM2Q_XMMu64_MASKmskw_AVX512	`EVEX.128.F3.0F38.W1 38 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVM2Q ymm, k` VPMOVM2Q_YMMu64_MASKmskw_AVX512	`EVEX.256.F3.0F38.W1 38 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVM2Q zmm, k` VPMOVM2Q_ZMMu64_MASKmskw_AVX512	`EVEX.512.F3.0F38.W1 38 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, k` `ymm, k`	`zmm, k`
Skylake-SP, Ice Lake, Sapphire Rapids	1 / 0.33p015	1 / 0.5p05
Zen 4	0 / 0.17	0 / 0.17

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

From a mask: each bit of k2 becomes a whole quadword, all ones for 1 and zero for 0.

Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms.

Result quadword i comes from bit i of k2. Result quadwords 1 to 0: a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    zmm1.q[i] = -1 if k2[i] else 0  # all ones or zero
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVM2Q xmm, k` `VPMOVM2Q ymm, k` `VPMOVM2Q zmm, k`
`xmm, ymm, zmm`	explicit	write
`k`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVM2Q, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movm_epi64` `__m128i _mm_movm_epi64(__mmask8 __A)`	`VPMOVM2Q xmm, k` EVEX.128 -mavx512vl -mavx512dq
`_mm256_movm_epi64` `__m256i _mm256_movm_epi64(__mmask8 __A)`	`VPMOVM2Q ymm, k` EVEX.256 -mavx512vl -mavx512dq
`_mm512_movm_epi64` `__m512i _mm512_movm_epi64(__mmask8 __A)`	`VPMOVM2Q zmm, k` EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512DQ_256` AVX10.1	Same as `AVX512DQ_128`	Same as `AVX512DQ_128`
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Same as `AVX512DQ_128`

AVX512DQ_128