VPMOVM2W instruction (AVX10.1)

VPMOVM2W turns a mask register into a vector of words: word i becomes FFFFh where bit i of the mask is 1 and 0 where it is 0, for 8, 16 or 32 words, and the register is cleared above the vector length. It is the word form of VPMOVM2B, whose page explains why AVX-512 code needs it: its compares write masks, where C and the older compares such as VPCMPEQW want vectors. It needs AVX512BW; VPMOVW2M goes the other way.

Recorded on Zen 5

Eight words. vpmovm2w xmm14, k2, with 9Ch in the low byte of K2, wrote FFFFh to words 2, 3, 4 and 7 and cleared the rest of ZMM14.
Sixteen. vpmovm2w ymm0, k4, low word 1D06h, set words 1, 2, 8, 10, 11 and 12.
Thirty-two. vpmovm2w zmm9, k6 set the words of the set bits of 21E7A709h and read none of bits 63:32.

In compiled code

For a == b on 64-byte vector types of short, GCC 14 and Clang 23 at -O2 with -march=x86-64-v4 compare into K0, GCC with VPCMPW and Clang with the EVEX VPCMPEQW, and build the vector with VPMOVM2W; on 32-byte vectors both use the VEX VPCMPEQW, which writes it directly. For a < 0 Clang needs neither: an arithmetic shift right by 15, VPSRAW, copies each sign bit over its word, while GCC compares with zero and uses VPMOVM2W. In a loop storing -(a[i] < b[i]) over short arrays GCC writes all ones under the compare mask with a zero-masked VMOVDQU16, and Clang uses the VEX compare on YMM registers. _mm512_movm_epi16 is KMOVD and VPMOVM2W in both.

AMD’s Zen 5 latency spreadsheet lists VPMOVM2W as one macro-op with a latency of one cycle on any of the four pipes FP0 to FP3, four per cycle, as VPMOVM2B.

Forms

Every encoding of VPMOVM2W that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVM2W xmm, k` VPMOVM2W_XMMu16_MASKmskw_AVX512	`EVEX.128.F3.0F38.W1 28 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVM2W ymm, k` VPMOVM2W_YMMu16_MASKmskw_AVX512	`EVEX.256.F3.0F38.W1 28 /r`	AVX10.1 or AVX512BW + AVX512VL
`VPMOVM2W zmm, k` VPMOVM2W_ZMMu16_MASKmskw_AVX512	`EVEX.512.F3.0F38.W1 28 /r`	AVX10.1 or AVX512BW

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`xmm, k` `ymm, k`	`zmm, k`
Skylake-SP, Ice Lake	1 / 0.33p015	1 / 0.5p05
Sapphire Rapids	3 / 0.33p015	3 / 0.5p05
Zen 4	0 / 0.17	0 / 0.17

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

From a mask: each bit of k2 becomes a whole word, all ones for 1 and zero for 0.

Every word works alike: 8, 16 and 32 words in the xmm, ymm and zmm forms.

Result word i comes from bit i of k2. Result words 7 to 0: a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    zmm1.w[i] = -1 if k2[i] else 0  # all ones or zero
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVM2W xmm, k` `VPMOVM2W ymm, k` `VPMOVM2W zmm, k`
`xmm, ymm, zmm`	explicit	write
`k`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVM2W, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movm_epi16` `__m128i _mm_movm_epi16(__mmask8 __A)`	`VPMOVM2W xmm, k` EVEX.128 -mavx512vl -mavx512bw
`_mm256_movm_epi16` `__m256i _mm256_movm_epi16(__mmask16 __A)`	`VPMOVM2W ymm, k` EVEX.256 -mavx512vl -mavx512bw
`_mm512_movm_epi16` `__m512i _mm512_movm_epi16(__mmask32 __A)`	`VPMOVM2W zmm, k` EVEX.512 -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512BW_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512BW_256` AVX10.1	Same as `AVX512BW_128`	Same as `AVX512BW_128`
`AVX512BW_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512BW `CPUID.(EAX=07H,ECX=0):EBX[30]` AVX512BW	Same as `AVX512BW_128`

AVX512BW_128