VPMOVMSKB instruction (AVX, AVX2)

VPMOVMSKB is PMOVMSKB in a VEX encoding: it collects the top bit of every byte of a vector register into a general-purpose register. The PMOVMSKB page covers the uses, from finding the first matching byte to testing text for ASCII. The VEX.256 form, from AVX2, is what this page adds: it reads a YMM register and gives 32 bits, so one instruction covers 32 bytes of a string scan. The VEX.128 form gives the same 16 bits as PMOVMSKB.

The result fills bits 31:0 or 15:0 and every bit above them becomes zero, in a 64-bit register too. On Zen 5, vpmovmskb esi, ymm8 turned RSI from 5E515D7066B8FE94h into 2D420B50h. A 32-bit mask with its top bit set is therefore a positive 64-bit number, and TZCNT or LZCNT on the 32-bit register is what finds the first or last byte.

In compiled code

With -march=x86-64-v3, GCC 14 and Clang 23 at -O2 compile a search for a byte in 32 bytes, written with _mm256_cmpeq_epi8 and _mm256_movemask_epi8, to VPBROADCASTB, VPCMPEQB with the data as its memory operand, VPMOVMSKB and TZCNT.

AVX-512 has no EVEX form. Its byte comparisons write a mask register, and with -march=x86-64-v4 Clang 23 rewrites the same intrinsics into VPCMPEQB into K0 and KMOVD to a general-purpose register, while GCC 14 keeps VPCMPEQB into a vector and VPMOVMSKB. Where the bits come straight from data, as in testing 32 bytes for ASCII with _mm256_movemask_epi8 of a load, both keep VPMOVMSKB at either target. VPMOVB2M is AVX-512’s way to collect the top bits into a mask register instead.

AMD’s latency spreadsheet for Zen 5 lists VPMOVMSKB as one macro-op on pipe 4 or 5, two per cycle. Zen 5’s two recorded cases, one per form, read XMM4 into R9D and YMM8 into ESI.

Forms

Every encoding of VPMOVMSKB that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVMSKB r32, xmm` VPMOVMSKB_GPR32d_XMMdq	`VEX.128.66.0F.WIG D7 /r`	AVX
`VPMOVMSKB r32, ymm` VPMOVMSKB_GPR32d_YMMqq	`VEX.256.66.0F.WIG D7 /r`	AVX2

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each byte of the source sets one bit of r32, bit i for byte i; the bits above them are cleared.

Shown: bytes 7 to 0. Every byte works alike: 16 and 32 bytes in the xmm and ymm forms.

Bit i of r32 comes from byte i of xmm2. Result bits 7 to 0: r7, r6, r5, r4, r3, r2, r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

r = 0
for i in range(VL // 8):
    r |= (ymm2.sb[i] < 0) << i
dest.write(r)  # the other bits are cleared

Run on AMD Zen 5 (EPYC 9645): 2 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVMSKB r32, xmm` `VPMOVMSKB r32, ymm`
`r32`	explicit	write
`xmm, ymm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: avx-type-7

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVMSKB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm_movemask_epi8` `int _mm_movemask_epi8(__m128i __a)`	`VPMOVMSKB r32, xmm` VEX.128 -mavxwith AVX enabled
`_mm_movepi8_mask` `__mmask16 _mm_movepi8_mask(__m128i __A)`	`VPMOVMSKB r32, xmm` VEX.128 -mavx512vl -mavx512bw
`_mm256_movemask_epi8` `int _mm256_movemask_epi8(__m256i __a)`	`VPMOVMSKB r32, ymm` VEX.256 -mavx2
`_mm256_movepi8_mask` `__mmask32 _mm256_movepi8_mask(__m256i __A)`	`VPMOVMSKB r32, ymm` VEX.256 -mavx512vl -mavx512bw

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set	CPUID	Processors
`AVX` AVX	AVX `CPUID.01H:ECX[28]` AVX	Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
`AVX2` AVX2	AVX2 `CPUID.(EAX=07H,ECX=0):EBX[5]` AVX2	Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

In compiled code#