VPMOVQ2M instruction (AVX10.1)

VPMOVQ2M copies bit 63 of every quadword of a vector into a mask register: 2, 4 or 8 bits for the XMM, YMM and ZMM forms, the mask bits above cleared. It is the quadword form of VPMOVD2M and VPMOVB2M, whose page explains the uses; VPMOVM2Q goes the other way. It came with AVX512DQ. For doubles the bit is the sign, the one VMOVMSKPD moves to a general-purpose register, and for int64_t it marks the negative elements, which AVX2 can test only with a signed compare against zero.

Recorded on Zen 5

One element. {evex} vpmovq2m k6, ymm0 read 10h, 8, 8000000000000000h and 0 and wrote 4, clearing the other 63 bits of K6.
ZMM. vpmovq2m k4, zmm17 gave A1h for 8000000000000000h at element 0 and FFFFFFFFFFFFFFFFh at elements 5 and 7; 0 and 1 gave 0.
XMM. For 0 and 1, {evex} vpmovq2m k1, xmm14 wrote 0.

In compiled code

At -O2 with -march=x86-64-v4, GCC 14 and Clang 23 test the signs of int64_t elements with compares, not with VPMOVQ2M: q[i] < 0 ? x[i] : y[i] is VPCMPQ with predicate 1 and VPBLENDMQ in GCC, and VPCMPGTQ against zero in Clang. Only _mm512_movepi64_mask gives VPMOVQ2M, followed by KMOVB in GCC and KMOVD in Clang; _mm256_movemask_pd stays VMOVMSKPD.

AMD’s Zen 5 latency spreadsheet gives one macro-op on pipe FP1 or FP2 and 3, 4 and 6 cycles for XMM, YMM and ZMM sources, as for VPMOVD2M.

Forms

Every encoding of VPMOVQ2M that Intel XED knows, one row per XED instruction form (iform). How to read the notation.

Instruction	Encoding	Requires
`VPMOVQ2M k, xmm` VPMOVQ2M_MASKmskw_XMMu64_AVX512	`EVEX.128.F3.0F38.W1 39 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVQ2M k, ymm` VPMOVQ2M_MASKmskw_YMMu64_AVX512	`EVEX.256.F3.0F38.W1 39 /r`	AVX10.1 or AVX512DQ + AVX512VL
`VPMOVQ2M k, zmm` VPMOVQ2M_MASKmskw_ZMMu64_AVX512	`EVEX.512.F3.0F38.W1 39 /r`	AVX10.1 or AVX512DQ

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.

Model	`k, xmm` `k, ymm` `k, zmm`
Skylake-SP, Ice Lake	1 / 1p0
Sapphire Rapids	3 / 1p0
Zen 4	1 / 1ALU0 ALU1 ALU2 ALU3

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

To a mask: each quadword of the source sets one bit of k1, bit i for quadword i.

Every quadword works alike: 2, 4 and 8 quadwords in the xmm, ymm and zmm forms.

Bit i of k1 comes from quadword i of xmm2. Result bits 1 to 0: r1, r0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    k1[i] = zmm2.sq[i] < 0
# the other bits of k1 are cleared

Run on AMD Zen 5 (EPYC 9645): 3 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.

Operand	Kind	Action
`VPMOVQ2M k, xmm` `VPMOVQ2M k, ymm` `VPMOVQ2M k, zmm`
`k`	explicit	write
`xmm, ymm, zmm`	explicit	read

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

All forms: AVX512-E7NM

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVQ2M, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

Intrinsic	Compiles to
`_mm512_movepi64_mask` `__mmask8 _mm512_movepi64_mask(__m512i __A)`	`VPMOVQ2M k, zmm` EVEX.512 -mavx512dq

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.

ISA set CPUID Processors

ISA set	CPUID	Processors
`AVX512DQ_128` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ + AVX512VL `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[31]` AVX512VL	Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
`AVX512DQ_256` AVX10.1	Same as `AVX512DQ_128`	Same as `AVX512DQ_128`
`AVX512DQ_512` AVX10.1	AVX10.1 `CPUID.(EAX=07H,ECX=1):EDX[19]` AVX10 `CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1` AVX10 version or AVX512DQ `CPUID.(EAX=07H,ECX=0):EBX[17]` AVX512DQ	Same as `AVX512DQ_128`

AVX512DQ_128