VPMOVQB

VPMOVQB narrows each quadword to a byte by keeping its low 8 bits: 8 quadwords of a ZMM register become 8 bytes, 4 from a YMM register and 2 from an XMM one. It is the widest step of AVX-512F’s down conversions: VPMOVDB describes the family, the masked narrowing store and the saturating siblings, which here are VPMOVSQB and VPMOVUSQB, and VPMOVQD the quadword form that halves the width.

A small result#

With an eighth of the source width, the result fills at most a quadword. The register form writes it to the low 8, 4 or 2 bytes of an XMM register and zeroes everything above, even under a merge mask: on Zen 5, vpmovqb xmm0{k4}, zmm31 wrote the five bytes K4 selected, kept the old values of bytes 1, 3 and 4, and cleared bytes 8 to 63. The memory form stores 8, 4 or 2 bytes. Under a mask it writes only the selected ones: with K4 again, the quadword store changed bytes 0, 2, 5, 6 and 7 and left the others alone, and a word store whose two mask bits were clear wrote nothing. The truncation itself drops 56 bits: 0000000000000100h and 8000000000000000h became 00h, and 7FFFFFFFFFFFFFFFh became FFh.

In compiled code#

For d[i] = (uint8_t)a[i] over uint64_t arrays, Clang 23 at -O2 with -march=x86-64-v4 loads YMM registers and stores 4 bytes from each with vpmovqb dword ptr [rdi + rax], ymm0; with a clamp to -128 and 127 it stores with VPMOVSQB instead. GCC 14 avoids the instruction: it gathers the low words of eight ZMM registers with VPERMT2D and VPERMT2W, narrows them to bytes with VPMOVWB and stores 64 bytes at once, after VPMINSQ and VPMAXSQ for the clamped loop. The intrinsics _mm512_cvtepi64_epi8 and _mm512_mask_cvtepi64_storeu_epi8 compile to the register and masked memory forms in both compilers.

AMD’s latency spreadsheet for Zen 5 lists VPMOVQB as it lists VPMOVDB: one macro-op with a latency of 2, 4 and 5 cycles for XMM, YMM and ZMM sources, and two macro-ops for the memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.b[i] = zmm2.q[i]  # the low bits
    elif zeroing:
        xmm1.b[i] = 0
    # else: xmm1.b[i] keeps its value
for i in range(VL // 64, 16):
    xmm1.b[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 64):
    if k1[i]:
        mem.b[i] = zmm2.q[i]  # the low bits
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMAXUD
• VPMAXUQ
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB

All 686 AVX10.1 instructions