VPMOVQW

VPMOVQW narrows each quadword to a word by keeping its low 16 bits: 8 quadwords of a ZMM register become 8 words, 128 bits, in an XMM register or in memory, 4 from a YMM register and 2 from an XMM one. It is the word form of VPMOVQB, whose page explains the small result and the masked store, between it and VPMOVQD; VPMOVSQW and VPMOVUSQW saturate instead. It is part of AVX-512F.

Recorded on Zen 5#

• Truncation can flip the sign. {evex} vpmovqw qword ptr [mem], ymm1 turned 8000h, 8001h, FFFFFFFFFFFF8000h and FFFFFFFFFFFF7FFFh into 8000h, 8001h, 8000h and 7FFFh: -32769 became 32767.
• The upper part is cleared, even under a merge mask. vpmovqw xmm7{k6}, zmm12, with A4h in the low byte of K6, wrote words 2, 5 and 7, kept the other five and zeroed bits 511:128.
• Register form from XMM. vpmovqw xmm1, xmm2 wrote 7FFFh and FFFFh and cleared XMM1 above bit 31.

In compiled code#

For d[i] = (uint16_t)a[i] over int64_t and uint16_t arrays, Clang 23 at -O2 with -march=x86-64-v4 loads 4 quadwords at a time into YMM registers and stores 4 words with vpmovqw qword ptr [...], ymm0, also in a loop of unknown length. GCC 14 avoids it, as for VPMOVQB: two VPERMT2D and a VPERMT2W gather the low words of four ZMM loads for one 64-byte store, and the loop of unknown length goes one element at a time. Both compile _mm512_cvtepi64_epi16 to vpmovqw xmm0, zmm0.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2, 4 and 5 cycles from XMM, YMM and ZMM sources, and the memory forms two macro-ops, with 3, 5 and 6 cycles, as VPMOVQB.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.w[i] = zmm2.q[i]  # the low bits
    elif zeroing:
        xmm1.w[i] = 0
    # else: xmm1.w[i] keeps its value
for i in range(VL // 64, 8):
    xmm1.w[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 64):
    if k1[i]:
        mem.w[i] = zmm2.q[i]  # the low bits
    # else: mem.w[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVQW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB

All 686 AVX10.1 instructions