VPMOVSDB

VPMOVSDB narrows signed doublewords to signed bytes, clamping each to -128 to 127: 16 from a ZMM register, 8 from a YMM register or 4 from an XMM register, into the low bytes of an XMM register or straight to memory. VPMOVDB, whose page covers the family, the masked store and the register form’s zeroed upper bytes, keeps the low byte instead. The cases recorded on Zen 5 show the clamp at its edges:

One step instead of two#

Before AVX-512 the same result takes two packs: PACKSSDW saturates doublewords to words and PACKSSWB words to bytes, and since a value clamped to -32768 to 32767 clamps to the same byte as the original, the two steps give what VPMOVSDB gives in one. The packs take two sources and interleave their results by 128-bit lane, though, so wider vectors need a VPERMQ or a different element order afterwards.

For d[i] = x < -128 ? -128 : x > 127 ? 127 : x over int32_t and int8_t arrays, Clang 23 at -O2 recognizes the clamp:

• with -march=x86-64-v4 it stores each 8 results with vpmovsdb qword ptr [rdi + rdx], ymm0, with no compare or blend;
• with -march=x86-64-v3 it uses VPACKSSDW and VPACKSSWB on XMM registers.

GCC 14 keeps the loop scalar at -O2 for either target, clamping one value at a time with VPMINSD and VPMAXSD.

In memory#

Under a write mask, the memory form stores only the selected bytes and leaves the others in memory as they were, which the recorded cases show too; the register form merges or zeroes the unselected bytes. The intrinsics are _mm512_cvtsepi32_epi8 for the register form and _mm512_mask_cvtsepi32_storeu_epi8 for the masked store, with 128- and 256-bit kin. VPMOVUSDB saturates to 0 to 255 instead, and treats the source as unsigned.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        xmm1.b[i] = ssat(zmm2.sd[i], 8)
    elif zeroing:
        xmm1.b[i] = 0
    # else: xmm1.b[i] keeps its value
for i in range(VL // 32, 16):
    xmm1.b[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 32):
    if k1[i]:
        mem.b[i] = ssat(zmm2.sd[i], 8)
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSDB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMINSB
• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD

All 686 AVX10.1 instructions