VPMOVSDW

VPMOVSDW narrows signed doublewords to words with signed saturation: a value above 32767 becomes 7FFFh and one below -32768 becomes 8000h. 16 doublewords of a ZMM register become 16 words in a YMM register or in memory, 8 from a YMM register and 4 from an XMM one. It is the saturating form of VPMOVDW, whose page shows the truncating narrowing store and the zeroed upper part of the register form; VPMOVUSDW saturates unsigned values instead, and VPMOVSDB narrows to bytes. It is part of AVX-512F.

Recorded on Zen 5#

• Both limits. {evex} vpmovsdw xmmword ptr [mem], ymm7 turned FFFFFFFFh, 00007FFFh, 00008000h and 0000FFFFh into FFFFh, 7FFFh, 7FFFh and 7FFFh, and FFFF8000h and FFFF7FFFh into 8000h and 8000h: -1 and -32768 fit, 32768 and -32769 do not.
• Register form. vpmovsdw xmm0, xmm31 wrote its four words and cleared XMM0 above bit 63.
• Masked store. vpmovsdw qword ptr [mem]{k7}, with bits 0 and 1 of the four that count set in K7, wrote 0055h and 0000h and left the other two words of memory as they were.

In compiled code#

For d[i] set to a[i] clamped to -32768 and 32767, over int32_t and int16_t arrays, Clang 23 at -O2 with -march=x86-64-v4 loads 8 doublewords at a time and stores 8 words with vpmovsdw xmmword ptr [...], ymm0, also in a loop of unknown length. GCC 14 clamps with VPMAXSD and VPMINSD and joins two ZMM registers with VPERMT2W, as VPMOVDW’s page shows, and handles the loop of unknown length one element at a time. Both compile _mm512_cvtsepi32_epi16 and _mm512_mask_cvtsepi32_storeu_epi16 to the register and masked memory forms. The older way, two sources at once, is PACKSSDW.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2 cycles from an XMM source and 4 from a YMM or ZMM one, and the memory forms two macro-ops, 5 cycles from a YMM or ZMM register, as VPMOVDW.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        ymm1.w[i] = ssat(zmm2.sd[i], 16)
    elif zeroing:
        ymm1.w[i] = 0
    # else: ymm1.w[i] keeps its value
for i in range(VL // 32, 8):
    ymm1.w[i] = 0
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

for i in range(VL // 32):
    if k1[i]:
        mem.w[i] = ssat(zmm2.sd[i], 16)
    # else: mem.w[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSDW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMINSD
• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ

All 686 AVX10.1 instructions