VPMOVSQB

VPMOVSQB narrows signed quadwords to signed bytes, clamping each to -128 to 127: 8 quadwords of a ZMM register become 8 bytes, 4 come from a YMM register and 2 from an XMM one, into the low bytes of an XMM register or straight to memory. It is the saturating form of VPMOVQB, which keeps the low byte instead and whose page shows the small result and the masked store, and the quadword form of VPMOVSDB. VPMOVUSQB clamps unsigned values to 255, and VPMOVSQW and VPMOVSQD narrow to words and doublewords. It is part of AVX-512F.

Recorded on Zen 5#

• Both limits. {evex} vpmovsqb dword ptr [mem], ymm1 turned FFh, 100h, 8000000000000000h and 7FFFFFFFFFFFFFFFh into 7Fh, 7Fh, 80h and 7Fh.
• Merging. vpmovsqb xmm9{k5}, zmm9, with E1h in the low byte of K5, wrote bytes 0, 5, 6 and 7: 1 stayed 01h, -128 and -129 both gave 80h and 255 gave 7Fh. Bytes 1 to 4 kept their old values and the rest of the register was cleared.
• Masked store. A word store with only the first of its two mask bits set in K4 wrote 7Fh for 7FFFFFFFFFFFFFFFh and left the second byte of memory as it was.

In compiled code#

For d[i] set to a[i] clamped to -128 and 127, over int64_t and int8_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 4 results with vpmovsqb dword ptr [rax + rdx], ymm0. GCC 14 clamps with VPMINSQ and VPMAXSQ, then gathers the low parts with VPERMT2D and VPERMT2W and narrows them with VPMOVWB, as VPMOVQB’s page shows. Both compile _mm512_cvtsepi64_epi8 to vpmovsqb xmm0, zmm0.

AMD’s Zen 5 latency spreadsheet lists VPMOVSQB as VPMOVQB: one macro-op on pipe FP1 or FP2 with 2, 4 and 5 cycles from XMM, YMM and ZMM sources, and two macro-ops for the memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.b[i] = ssat(zmm2.sq[i], 8)
    elif zeroing:
        xmm1.b[i] = 0
    # else: xmm1.b[i] keeps its value
for i in range(VL // 64, 16):
    xmm1.b[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 64):
    if k1[i]:
        mem.b[i] = ssat(zmm2.sq[i], 8)
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMINSQ
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW

All 686 AVX10.1 instructions