VPMOVSQD

VPMOVSQD narrows signed quadwords to doublewords, clamping each to the int32_t range, 80000000h to 7FFFFFFFh: 8 quadwords of a ZMM register become 8 doublewords in a YMM register or in memory, 4 come from a YMM register and 2 from an XMM one. It is the saturating form of VPMOVQD, the C cast that keeps the low half, whose page also shows how AVX2 code does without either. VPMOVUSQD clamps unsigned values to FFFFFFFFh, and VPMOVSQW and VPMOVSQB narrow further. It is part of AVX-512F.

Recorded on Zen 5#

• One past each end. {evex} vpmovsqd xmm17, xmm30 turned 80000001h, 2^31 + 1, into 7FFFFFFFh and FFFFFFFF80000000h, -2^31, into 80000000h, and cleared XMM17 above bit 63.
• Merging. vpmovsqd ymm0{k6}, zmm31, with A4h in the low byte of K6, wrote doublewords 2, 5 and 7: 80000000h for -2^31 - 1 and for 8000000000000000h, and 00000055h. The others kept YMM0’s old values, and bits 511:256 were cleared.
• Masked store. vpmovsqd ymmword ptr [mem]{k2}, zmm24, with C9h in the low byte of K2, wrote 80000000h for 8000000000000000h, then 0, and 7FFFFFFFh for both 7FFFFFFFh and 80000000h, and left the other four doublewords of memory alone.

In compiled code#

For d[i] set to a[i] clamped to INT32_MIN and INT32_MAX, over int64_t and int32_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 4 results with vpmovsqd xmmword ptr [rdx + 4*rax], ymm0. GCC 14 clamps with VPMINSQ and VPMAXSQ, then picks the even doublewords of two ZMM registers with one VPERMT2D, as VPMOVQD’s page shows. Both compile _mm512_cvtsepi64_epi32 to vpmovsqd ymm0, zmm0.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2 cycles from an XMM source and 4 from a YMM or ZMM one, and the memory forms two macro-ops, with 3 and 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        ymm1.d[i] = ssat(zmm2.sq[i], 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

for i in range(VL // 64):
    if k1[i]:
        mem.d[i] = ssat(zmm2.sq[i], 32)
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSQD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ

All 686 AVX10.1 instructions