x86-64.net

Instruction

VPMOVSQW

Narrows packed signed quadwords to words with signed saturation.

Extensions
Forms
6 (6 EVEX)
Data
Intel XED v2026.08.23

Forms

Every encoding of VPMOVSQW that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMOVSQW xmm {k}{z}, zmm VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512EVEX.512.F3.0F38.W0 24 /rAVX10.1 or AVX512F
VPMOVSQW m128 {k}, zmm VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512EVEX.512.F3.0F38.W0 24 /rAVX10.1 or AVX512F
VPMOVSQW xmm {k}{z}, xmm VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512EVEX.128.F3.0F38.W0 24 /rAVX10.1 or AVX512F + AVX512VL
VPMOVSQW m32 {k}, xmm VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512EVEX.128.F3.0F38.W0 24 /rAVX10.1 or AVX512F + AVX512VL
VPMOVSQW xmm {k}{z}, ymm VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512EVEX.256.F3.0F38.W0 24 /rAVX10.1 or AVX512F + AVX512VL
VPMOVSQW m64 {k}, ymm VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512EVEX.256.F3.0F38.W0 24 /rAVX10.1 or AVX512F + AVX512VL

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSQW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtsepi64_epi16 __m128i _mm_cvtsepi64_epi16(__m128i __A)

VPMOVSQW xmm, xmm EVEX.128 -mavx512vl

_mm_mask_cvtsepi64_epi16 __m128i _mm_mask_cvtsepi64_epi16(__m128i __O, __mmask8 __M, __m128i __A)

VPMOVSQW xmm {k}, xmm EVEX.128 -mavx512vl

_mm_mask_cvtsepi64_storeu_epi16 void _mm_mask_cvtsepi64_storeu_epi16(void *__P, __mmask8 __M, __m128i __A)

VPMOVSQW m32 {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_cvtsepi64_epi16 __m128i _mm_maskz_cvtsepi64_epi16(__mmask8 __M, __m128i __A)

VPMOVSQW xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_cvtsepi64_epi16 __m128i _mm256_cvtsepi64_epi16(__m256i __A)

VPMOVSQW xmm, ymm EVEX.256 -mavx512vl

_mm256_mask_cvtsepi64_epi16 __m128i _mm256_mask_cvtsepi64_epi16(__m128i __O, __mmask8 __M, __m256i __A)

VPMOVSQW xmm {k}, ymm EVEX.256 -mavx512vl

_mm256_mask_cvtsepi64_storeu_epi16 void _mm256_mask_cvtsepi64_storeu_epi16(void *__P, __mmask8 __M, __m256i __A)

VPMOVSQW m64 {k}, ymm EVEX.256 -mavx512vl

_mm256_maskz_cvtsepi64_epi16 __m128i _mm256_maskz_cvtsepi64_epi16(__mmask8 __M, __m256i __A)

VPMOVSQW xmm {k}{z}, ymm EVEX.256 -mavx512vl

_mm512_cvtsepi64_epi16 __m128i _mm512_cvtsepi64_epi16(__m512i __A)

VPMOVSQW xmm, zmm EVEX.512 -mavx512f

_mm512_mask_cvtsepi64_epi16 __m128i _mm512_mask_cvtsepi64_epi16(__m128i __O, __mmask8 __M, __m512i __A)

VPMOVSQW xmm {k}, zmm EVEX.512 -mavx512f

_mm512_mask_cvtsepi64_storeu_epi16 void _mm512_mask_cvtsepi64_storeu_epi16(void *__P, __mmask8 __M, __m512i __A)

VPMOVSQW m128 {k}, zmm EVEX.512 -mavx512f

_mm512_maskz_cvtsepi64_epi16 __m128i _mm512_maskz_cvtsepi64_epi16(__mmask8 __M, __m512i __A)

VPMOVSQW xmm {k}{z}, zmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, which covers AMD processors up to Zen 2.
ISA setCPUIDProcessors in XED
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids
AVX512F_256

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model.
  2. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  3. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.