VPMOVSQW

VPMOVSQW narrows signed quadwords to words, clamping each to -32768 to 32767: 8 quadwords of a ZMM register become 8 words in an XMM register or in memory, 4 come from a YMM register and 2 from an XMM one. It is the saturating form of VPMOVQW, which keeps the low word, and the quadword form of VPMOVSDW. VPMOVUSQW clamps unsigned values to 65535, and VPMOVSQB narrows to bytes. The register form zeroes the destination above the words it writes, as on VPMOVDB’s page. It is part of AVX-512F.

Recorded on Zen 5#

• Both limits. {evex} vpmovsqw qword ptr [mem], ymm0 turned -1, 7FFFh, 8000h and 8001h into FFFFh, 7FFFh, 7FFFh and 7FFFh: 32768 is one too many.
• Register form. {evex} vpmovsqw xmm7, xmm12 turned 8000000000000000h and 7FFFFFFFFFFFFFFFh into 8000h and 7FFFh and cleared XMM7 above bit 31.
• Masked store. vpmovsqw xmmword ptr [mem]{k2}, zmm7, with C9h in the low byte of K2, wrote words 0, 3, 6 and 7: 8000h for -32769 and for 8000000000000000h, then 0000h and 0001h. The other four words of memory kept their values, among them the slot of FFFFh, which would have become 7FFFh.

In compiled code#

For d[i] set to a[i] clamped to -32768 and 32767, over int64_t and int16_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 4 results with vpmovsqw qword ptr [rdx + 2*rax], ymm0. GCC 14 clamps with VPMINSQ and VPMAXSQ and joins the low words of four ZMM registers with VPERMT2D and VPERMT2W. Both compile _mm512_cvtsepi64_epi16 to vpmovsqw xmm0, zmm0.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2, 4 and 5 cycles from XMM, YMM and ZMM sources, and the memory forms two macro-ops, with 3, 5 and 6.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.w[i] = ssat(zmm2.sq[i], 16)
    elif zeroing:
        xmm1.w[i] = 0
    # else: xmm1.w[i] keeps its value
for i in range(VL // 64, 8):
    xmm1.w[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 64):
    if k1[i]:
        mem.w[i] = ssat(zmm2.sq[i], 16)
    # else: mem.w[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSQW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMINUB
• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD

All 686 AVX10.1 instructions