Instruction
VPMOVSSDB
Narrows packed signed doublewords to bytes with symmetric saturation, to the range -127 to 127.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
VPMOVSSDB narrows signed doublewords to signed bytes as VPMOVSDB does, 4, 8 or 16 of them from an xmm, ymm or zmm register into the low bytes of an xmm register or straight to 4, 8 or 16 bytes of memory, but it clamps to -127 to 127, a range symmetric about zero: every value of -127 or less gives 81h, and no result is 80h, -128. It belongs to AVX10_V2_AUX of the ACE specification: opcode 41h with the F3 prefix in map 0F38, W0, where VPMOVSDB has 21h.
Why leave out -128
A byte of -128 has no positive counterpart: negating it gives -128 again, and the range -128 to 127 reaches one step further below zero than above. The ACE specification gives keeping the sign symmetry as the reason for the narrower range.
Its operands
As in VPMOVSDB, the source register is in ModRM.reg and the destination, register or memory, in ModRM.r/m. EVEX.vvvv must be 1111b, or the instruction raises #UD. A write mask has one bit per byte: the register form merges or zeroes the bytes it leaves out and clears the destination above the written bytes, while the memory form leaves them in memory as they were and takes no zeroing.
In our builds
Clang 23’s assembler and GNU as 2.44 reject the mnemonic, and ACE’s
intrinsic _mm512_cvtssepi32_epi8, one letter away from VPMOVSDB’s
_mm512_cvtsepi32_epi8, is missing from Clang 23’s headers. Without it,
one VPMAXSD against -127 before VPMOVSDB gives the
same bytes. For a loop clamping int32_t values to -127 to 127 into an
int8_t array, Clang 23 at -O2 with -march=x86-64-v4 clamps at both
ends with VPMAXSD and VPMINSD and then truncates with
VPMOVDB; GCC 14 also clamps at both ends and narrows
through VPERMT2W and VPMOVWB. This site’s recorded cases include none of
VPMOVSSDB.
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPMOVSSDB xmm {k}{z}, xmm
VPMOVSSDB_XMMu8_MASKmskw_XMMu32_AVX512 | EVEX.128.F3.0F38.W0 41 /r | AVX10_V2_AUX + AVX10 |
VPMOVSSDB m32 {k}, xmm
VPMOVSSDB_MEMu8_MASKmskw_XMMu32_AVX512 | EVEX.128.F3.0F38.W0 41 /r | AVX10_V2_AUX + AVX10 |
VPMOVSSDB xmm {k}{z}, ymm
VPMOVSSDB_XMMu8_MASKmskw_YMMu32_AVX512 | EVEX.256.F3.0F38.W0 41 /r | AVX10_V2_AUX + AVX10 |
VPMOVSSDB m64 {k}, ymm
VPMOVSSDB_MEMu8_MASKmskw_YMMu32_AVX512 | EVEX.256.F3.0F38.W0 41 /r | AVX10_V2_AUX + AVX10 |
VPMOVSSDB xmm {k}{z}, zmm
VPMOVSSDB_XMMu8_MASKmskw_ZMMu32_AVX512 | EVEX.512.F3.0F38.W0 41 /r | AVX10_V2_AUX + AVX10 |
VPMOVSSDB m128 {k}, zmm
VPMOVSSDB_MEMu8_MASKmskw_ZMMu32_AVX512 | EVEX.512.F3.0F38.W0 41 /r | AVX10_V2_AUX + AVX10 |
Data flow
Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.
Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 doublewords. The forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.
Result bytes 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.
A memory destination receives the bytes alone. Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 doublewords. The forms write under a mask: where its bit is 0, the element keeps its old value.
Result bytes 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.
Operation
What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.
for i in range(VL // 32):
if k1[i]:
sa = zmm2.sd[i]
xmm1.b[i] = max(-127, min(127, sa))
elif zeroing:
xmm1.b[i] = 0
# else: xmm1.b[i] keeps its value
for i in range(VL // 32, 16):
xmm1.b[i] = 0
# symmetric saturation: never -128
# xmm1 is zeroed from bit 128 upNot run on a processor: none of these processors has AVX10.2.
for i in range(VL // 32):
if k1[i]:
sa = zmm2.sd[i]
mem.b[i] = max(-127, min(127, sa))
# else: mem.b[i] is not written
# symmetric saturation: never -128Not run on a processor: none of these processors has AVX10.2.
Operands
| Operand | Kind | Action |
|---|---|---|
VPMOVSSDB xmm/m32 {k}{z}, xmm VPMOVSSDB xmm/m64 {k}{z}, ymm VPMOVSSDB xmm/m128 {k}{z}, zmm | ||
xmm/m32/64/128 | explicit | write (masked) |
{k} | explicit | read (write mask) |
xmm, ymm, zmm | explicit | read |
Flags
None: XED records no flag that the forms test or change.
Exceptions
The exception class is XED's name for the set of exception conditions that a form follows. How to read.
- Register forms
AVX512-E6NF- Memory forms
AVX512-E6
Attributes
What else XED records about the forms. How to read.
- All forms
- write masking
- Memory forms
- memory fault suppression
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors |
|---|---|---|
AVX10_V2_AUX_128 | AVX10_V2_AUX + AVX10 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
AVX10_V2_AUX_256 | Same as AVX10_V2_AUX_128 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
AVX10_V2_AUX_512 | Same as AVX10_V2_AUX_128 | None in XED’s chip model, which lists these instructions only under its placeholder for future processors. |
More AVX10_V2_AUX instructions
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model. - x86 Ecosystem Advisory Group: AI Compute Extensions (ACE) Specification, version 1.16.2 (July 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The text is our own.