VPMOVSWB

VPMOVSWB narrows signed words to bytes, clamping each to -128 to 127: 32 words of a ZMM register become 32 bytes in a YMM register or in memory, 16 come from a YMM register and 8 from an XMM one. It is the saturating form of VPMOVWB, whose page shows the masked store and the merge into a register, and the signed partner of VPMOVUSWB, which clamps unsigned words to 255. PACKSSWB clamps the same way but takes two sources and interleaves them by 128-bit lane. VPMOVSWB needs AVX512BW.

Recorded on Zen 5#

• Both limits. {evex} vpmovswb xmmword ptr [mem], ymm9 turned FF80h and FF7Fh, -128 and -129, into 80h, and 8000h into 80h too; 0080h, 0081h, 00FFh, 0100h and 7FFFh became 7Fh, while 007Fh and FFFFh, -1, fit and gave 7Fh and FFh.
• Register form. {evex} vpmovswb xmm9, xmm9 wrote its eight bytes, 80h, 7Fh, 7Fh, 80h, 7Fh, 55h, 00h and 01h, and cleared XMM9 above bit 63.
• Merging. vpmovswb ymm14{k1}, zmm8 wrote only the bytes K1 selected, kept the others and cleared bits 511:256.

In compiled code#

For d[i] set to a[i] clamped to -128 and 127, over int16_t and int8_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 16 results with vpmovswb xmmword ptr [rax + rdx], ymm0. GCC 14 clamps with VPMINSW and VPMAXSW, truncates with VPMOVWB and joins two halves with VINSERTI64X4. Both compile _mm512_cvtsepi16_epi8 to vpmovswb ymm0, zmm0.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2 cycles from an XMM source and 4 from a YMM or ZMM one, and the memory forms two macro-ops, 5 cycles from a YMM or ZMM register, as VPMOVWB.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:
        ymm1.b[i] = ssat(zmm2.sw[i], 8)
    elif zeroing:
        ymm1.b[i] = 0
    # else: ymm1.b[i] keeps its value
for i in range(VL // 16, 16):
    ymm1.b[i] = 0
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

for i in range(VL // 16):
    if k1[i]:
        mem.b[i] = ssat(zmm2.sw[i], 8)
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSWB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMINUD
• VPMINUQ
• VPMINUW
• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ

All 686 AVX10.1 instructions