x86-64.net

Instruction

VPMOVSXBD

Sign-extends packed bytes to doublewords.

Extensions
Forms
10 (4 VEX, 6 EVEX)
Data
Intel XED v2026.08.23

VPMOVSXBD widens signed bytes to doublewords: each byte becomes a 32-bit element holding the same value, its sign bit copied into the 24 bits above it, so -1 (FFh) becomes FFFFFFFFh and 7Fh stays 127. The result is four times as wide as the source, so the source is a quarter of a register: 4 bytes for an xmm result, 8 for ymm, 16 for zmm, from the low end of an XMM register or from memory of exactly that size, at any alignment. PMOVSXBD is the SSE4.1 form; the EVEX forms add a write mask with one bit per doubleword.

Like VPMOVZXBW, which widens unsigned bytes to words, it keeps the elements in order across lanes: vpmovsxbd ymm, xmm takes bytes 0 to 7 and spreads them over both 128-bit lanes.

One step or two

Signed bytes reach doubleword arithmetic in loops such as d[i] += b[i] with int8_t b[] and int32_t d[], or a conversion to float, where VPMOVSXBD is followed by VCVTDQ2PS. For arrays of 1,024 elements, GCC 14 and Clang 23 at -O2 take different paths:

  • Clang widens straight from memory, 8 bytes per ymm result with -march=x86-64-v3 and x86-64-v4, or 4 bytes per PMOVSXBD with -msse4.1.
  • GCC loads a full vector of bytes and widens in two steps, VPMOVSXBW to words and then VPMOVSXWD to doublewords, moving the upper halves down with VEXTRACTI128, or PSRLDQ under SSE4.1, so that it never emits VPMOVSXBD for these loops.
  • For the baseline, without SSE4.1, Clang interleaves each byte with itself twice with PUNPCKLBW and PUNPCKLWD, which leaves it in the top byte of a doubleword, and shifts it down with PSRAD by 24, which brings the sign along. GCC builds the sign bytes with PCMPGTB against zero and unpacks with them.

AMD’s Zen 5 guide lists the xmm and ymm forms as one macro-op with a latency of two cycles, and the zmm form with a latency of four.

VPMOVZXBD fills with zeros instead, and VPMOVSXBQ widens bytes to quadwords. The way back to bytes in AVX-512 is VPMOVDB, which truncates, or its saturating forms.

In the optimization guide

What the optimization guide says about VPMOVSXBD, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

  • Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Every encoding of VPMOVSXBD that Intel XED knows, one row per XED instruction form (iform). How to read the notation.
InstructionEncodingRequires
VPMOVSXBD xmm, xmm VPMOVSXBD_XMMdq_XMMdVEX.128.66.0F38.WIG 21 /rAVX
VPMOVSXBD xmm, m32 VPMOVSXBD_XMMdq_MEMdVEX.128.66.0F38.WIG 21 /rAVX
VPMOVSXBD ymm, xmm VPMOVSXBD_YMMqq_XMMqVEX.256.66.0F38.WIG 21 /rAVX2
VPMOVSXBD ymm, m64 VPMOVSXBD_YMMqq_MEMqVEX.256.66.0F38.WIG 21 /rAVX2
VPMOVSXBD zmm {k}{z}, xmm VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512EVEX.512.66.0F38.WIG 21 /rAVX10.1 or AVX512F
VPMOVSXBD zmm {k}{z}, m128 VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512EVEX.512.66.0F38.WIG 21 /rAVX10.1 or AVX512F
VPMOVSXBD xmm {k}{z}, xmm VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512EVEX.128.66.0F38.WIG 21 /rAVX10.1 or AVX512F + AVX512VL
VPMOVSXBD xmm {k}{z}, m32 VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512EVEX.128.66.0F38.WIG 21 /rAVX10.1 or AVX512F + AVX512VL
VPMOVSXBD ymm {k}{z}, xmm VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512EVEX.256.66.0F38.WIG 21 /rAVX10.1 or AVX512F + AVX512VL
VPMOVSXBD ymm {k}{z}, m64 VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512EVEX.256.66.0F38.WIG 21 /rAVX10.1 or AVX512F + AVX512VL

Latency and throughput

What the scheduling models of LLVM 23.1.2 give for each form, not measurements: latency / reciprocal throughput in cycles, the ports under them. A row is a model, or models that agree; a dash, a form that its processors lack. Memory forms: latency from the address, ports without the load and store units. Which processors each model covers.
Modelxmm, xmm
xmm {k}{z}, xmm		xmm, m32ymm, xmm
ymm {k}{z}, xmm		ymm, m64zmm {k}{z}, xmmzmm {k}{z}, m128
ymm {k}{z}, m64		xmm {k}{z}, m32
Sandy Bridge1 / 0.5p157 / 0.5p15
Haswell, Broadwell, Skylake1 / 1p56 / 1p53 / 1p58 / 1p5
Skylake-SP1 / 1p56 / 1p53 / 1p58 / 1p53 / 1p510 / 1p57 / 1p5
Ice Lake1 / 0.5p157 / 0.5p153 / 1p58 / 1p53 / 1p510 / 1p57 / 0.5p15
Alder Lake1 / 0.5p158 / 0.5p153 / 1p511 / 1p5
Sapphire Rapids1 / 0.5p158 / 0.5p153 / 1p511 / 1p53 / 1p511 / 1p58 / 0.5p15
Lunar Lake1 / 0.5V2 V38 / 0.5V2 V33 / 0.5V2 V310 / 2.33V2 V3
Piledriver2 / 1FPU1 FPXBR7 / 1.5FPU1 FPXBR
Zen1 / 0.5FPU1 FPU28 / 0.5FPU1 FPU21 / 2FPU1 FPU28 / 2FPU1 FPU2
Zen 21 / 0.5FPU1 FPU28 / 0.5FPU1 FPU24 / 0.5FPU1 FPU28 / 0.5FPU1 FPU2
Zen 31 / 0.5FP1 FP28 / 0.5FP1 FP24 / 1.5FP1 FP211 / 1.5FP1 FP2
Zen 42 / 0.5FP1 FP28 / 0.5FP1 FP22 / 0.5FP1 FP211 / 1.5FP1 FP24 / 1FP1 FP211 / 1.5FP1 FP28 / 0.5FP1 FP2
Jaguar1 / 0.5FPU0 FPU1 VALU0 VALU16 / 1FPU0 FPU1 VALU0 VALU1

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Widen: each byte becomes a doubleword, sign-extended, in the same order.
VPMOVSXBD: each element widenedResult doublewords 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.0123456789101112131415xmm2or m128a1111111111111110k1a0a1a2a3a4a5a6a7a8a9a10a11a12a13a15zmm1

The grey upper part of each doubleword is the extension: copies of the sign bit. Shown for the zmm form; the xmm and ymm forms work the same on 4 and 8 bytes. The EVEX forms write under a mask: where its bit is 0, the element keeps its old value, or zeroes it with {z}.

Result doublewords 15 to 0: a15, unchanged (bit 14 of k1 is 0), a13, a12, a11, a10, a9, a8, a7, a6, a5, a4, a3, a2, a1, a0.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:                   # 1 without a write mask
        zmm1.d[i] = src2.sb[i]  # sign-extended
    elif zeroing:
        zmm1.d[i] = 0
    # else: zmm1.d[i] keeps its value
# zmm1 is zeroed from bit VL up

Run on AMD Zen 5 (EPYC 9645): 10 cases.

Operands

What each form reads and writes, as Intel XED records it: the operands of its syntax, in order, and the implicit ones that the syntax does not name. How to read.
OperandKindAction
VPMOVSXBD xmm, xmm/m32 VPMOVSXBD ymm, xmm/m64
xmm, ymmexplicitwrite
xmm/m32/64explicitread
VPMOVSXBD xmm {k}{z}, xmm/m32 VPMOVSXBD ymm {k}{z}, xmm/m64 VPMOVSXBD zmm {k}{z}, xmm/m128
xmm, ymm, zmmexplicitwrite (masked)
{k}explicitread (write mask)
xmm/m32/64/128explicitread

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms
avx-type-5
EVEX forms
AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms
write masking
EVEX memory forms
memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSXBD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

IntrinsicCompiles to
_mm_cvtepi8_epi32 __m128i _mm_cvtepi8_epi32(__m128i __V)

VPMOVSXBD xmm, xmm VEX.128 -mavxwith AVX enabled

_mm_mask_cvtepi8_epi32 __m128i _mm_mask_cvtepi8_epi32(__m128i __W, __mmask8 __U, __m128i __A)

VPMOVSXBD xmm {k}, xmm EVEX.128 -mavx512vl

_mm_maskz_cvtepi8_epi32 __m128i _mm_maskz_cvtepi8_epi32(__mmask8 __U, __m128i __A)

VPMOVSXBD xmm {k}{z}, xmm EVEX.128 -mavx512vl

_mm256_cvtepi8_epi32 __m256i _mm256_cvtepi8_epi32(__m128i __V)

VPMOVSXBD ymm, xmm VEX.256 -mavx2

_mm256_mask_cvtepi8_epi32 __m256i _mm256_mask_cvtepi8_epi32(__m256i __W, __mmask8 __U, __m128i __A)

VPMOVSXBD ymm {k}, xmm EVEX.256 -mavx512vl

_mm256_maskz_cvtepi8_epi32 __m256i _mm256_maskz_cvtepi8_epi32(__mmask8 __U, __m128i __A)

VPMOVSXBD ymm {k}{z}, xmm EVEX.256 -mavx512vl

_mm512_cvtepi8_epi32 __m512i _mm512_cvtepi8_epi32(__m128i __A)

VPMOVSXBD zmm, xmm EVEX.512 -mavx512f

_mm512_mask_cvtepi8_epi32 __m512i _mm512_mask_cvtepi8_epi32(__m512i __W, __mmask16 __U, __m128i __A)

VPMOVSXBD zmm {k}, xmm EVEX.512 -mavx512f

_mm512_maskz_cvtepi8_epi32 __m512i _mm512_maskz_cvtepi8_epi32(__mmask16 __U, __m128i __A)

VPMOVSXBD zmm {k}{z}, xmm EVEX.512 -mavx512f

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

CPUID requirements and processors of the XED ISA sets above. Alternatives are separated by “or”; processors follow XED’s chip model, whose AMD processors end with Zen 2, and the CPU data of this site for Zen 3 to Zen 6.
ISA setCPUIDProcessors
AVX

AVX
CPUID.01H:ECX[28] AVX

Sandy Bridge, Ivy Bridge, Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Bulldozer, Piledriver, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX2

AVX2
CPUID.(EAX=07H,ECX=0):EBX[5] AVX2

Haswell, Broadwell, Skylake, Comet Lake, Cannon Lake, Ice Lake (client), Tiger Lake, Alder Lake, Arrow Lake, Panther Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Sierra Forest, Clearwater Forest, Knights Landing, Knights Mill, Zen, Zen+, Zen 2, Zen 3, Zen 4, Zen 5, Zen 6
AVX512F_512

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill, Zen 4, Zen 5, Zen 6
AVX512F_128

AVX10.1
CPUID.(EAX=07H,ECX=1):EDX[19] AVX10
CPUID.(EAX=24H,ECX=0):EBX[7:0] ≥ 1 AVX10 version

or

AVX512F + AVX512VL
CPUID.(EAX=07H,ECX=0):EBX[16] AVX512F
CPUID.(EAX=07H,ECX=0):EBX[31] AVX512VL

Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Zen 4, Zen 5, Zen 6
AVX512F_256
Same as AVX512F_128Same as AVX512F_128

More AVX instructions

All 253 AVX instructions

More AVX2 instructions

All 138 AVX2 instructions

More AVX10.1 instructions

All 686 AVX10.1 instructions

Sources

  1. Intel XED v2026.08.23 (commit 0bcb6237345c): forms, encodings, operands, flags, exception classes, attributes, ISA sets, CPUID bits and chip model.
  2. The CPU data of x86-64.net: Zen 3 to Zen 6, from GCC’s -march feature sets and AMD’s Processor Programming References, which the page of each processor cites.
  3. Clang's x86 intrinsic headers, LLVM 23.1.2 (commit 85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them.
  4. LLVM 23.1.2's x86 scheduling models (commit 85ac56026243): the latency, reciprocal throughput and ports of each form, as llvm-mca reports them.
  5. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 (325383-093, September 2026): Volume 2B, page 4-352 (PMOVSX)
  6. Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 1 (253665-093, September 2026)
  7. Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 7.0 (361050-007, April 2026)
  8. Software Optimization Guide for the AMD Zen5 Microarchitecture (58455, rev. 1.00, August 2024), Wayback Machine copy of AMD's ZIP

The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang and the timings from LLVM's scheduling models, both part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.