VPMOVSXBW

VPMOVSXBW is the VEX and EVEX form of SSE4.1’s PMOVSXBW, whose page covers the sign extension of bytes to words. The source is half the width of the result: 8 bytes for an xmm destination (AVX), 16 for ymm (AVX2) and 32 for zmm (AVX512BW; the EVEX xmm and ymm forms also need AVX512VL, or AVX10.1), from memory at any alignment. The bytes stay in order across lanes: on Zen 5, vpmovsxbw ymm12, xmm6 widened bytes 8 to 15 of XMM6, 80h, 7Fh, 80h, 7Fh, 00h, 0Fh, 10h and 08h, into the upper 128-bit lane as FF80h, 007Fh, FF80h, 007Fh, 0000h, 000Fh, 0010h and 0008h, and cleared bits 511:256 of ZMM12, which PMOVSXBW would keep.

Masks#

The EVEX forms add a write mask per word. The recorded vpmovsxbw zmm1{k2}, ymm2, with C9h in the low byte of k2, wrote words 0, 3, 6 and 7, FF80h, 0001h, 0001h and FFFFh from bytes 80h, 01h, 01h and FFh, and merged the others: words 1 and 2 kept 887Bh and A295h. vpmovsxbw xmm24{k6}{z}, qword ptr [mem] zeroed instead: with A4h in k6, only words 2, 5 and 7 were written, and every other bit of ZMM24 up to 511 was cleared.

In compiled code#

In our builds at -O2 over fixed-size int8_t arrays copied into int16_t ones, or multiplied pairwise into them with VPMULLW, Clang 23 widens 16 bytes at a time straight from memory with -march=x86-64-v3 and with x86-64-v4, on ymm registers either way. GCC 14 loads 32 bytes, widens the low half, moves the high half down with VEXTRACTI128 and widens it too; with -v4 it does the same at twice the width, each ymm half into a zmm register. Into int32_t, Clang uses VPMOVSXBD while GCC goes through words, VPMOVSXBW and then VPMOVSXWD.

AMD’s latency spreadsheet for Zen 5 gives the VEX row and the EVEX xmm and ymm row a latency of 2 cycles and the zmm row 4, one macro-op and two per cycle each. VPMOVZXBW fills with zeros instead.

In the optimization guide

What the optimization guide says about VPMOVSXBW, a line per claim. Each links to the claim in the guide, with its sources and where they differ.

Crestmont and Gracemont

• Vectors and AVX2: The 256-bit forms that widen or insert data loaded from memory take two dependent micro-ops.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 16):
    if k1[i]:                   # 1 without a write mask
        zmm1.w[i] = src2.sb[i]  # sign-extended
    elif zeroing:
        zmm1.w[i] = 0
    # else: zmm1.w[i] keeps its value
# zmm1 is zeroed from bit VL up

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

VEX forms

avx-type-5

EVEX forms

AVX512-E5

Attributes

What else XED records about the forms. How to read.

EVEX forms

write masking

EVEX memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVSXBW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX instructions

• VPINSRD
• VPINSRQ
• VPINSRW
• VPMADDUBSW
• VPMADDWD
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD

All 253 AVX instructions

More AVX2 instructions

• VPHSUBW
• VPMADDUBSW
• VPMADDWD
• VPMASKMOVD
• VPMASKMOVQ
• VPMAXSB
• VPMAXSD
• VPMAXSW
• VPMAXUB
• VPMAXUD
• VPMAXUW
• VPMINSB
• VPMINSD
• VPMINSW
• VPMINUB
• VPMINUD
• VPMINUW
• VPMOVMSKB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLW
• VPMULUDQ
• VPOR
• VPSADBW
• VPSHUFB
• VPSHUFD

All 138 AVX2 instructions

More AVX10.1 instructions

• VPMOVB2M
• VPMOVD2M
• VPMOVDB
• VPMOVDW
• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW

All 686 AVX10.1 instructions