VPMOVUSDB

VPMOVUSDB narrows unsigned doublewords to bytes, clamping each to 255: 16 from a ZMM register, 8 from a YMM register or 4 from an XMM register, into the low bytes of an XMM register or straight to memory. The VPMOVDB page covers the family, the masked store and the zeroed upper bytes of the register form.

Unsigned in, unsigned out#

The source is read as unsigned, so there is no lower clamp to hit: a negative int32_t is a large unsigned number and becomes 255, not 0. In the cases recorded on Zen 5, FFFFFF80h, FFFFFF7Fh, 80000000h, 7FFFFFFFh and 100h all became FFh, while 81h stayed 81h. To clamp signed values to 0 to 255, raise the negative ones to zero first, with VPMAXSD against a zero register, as the VPMOVDB page shows Clang doing.

The SSE packs work the other way round: PACKUSDW and PACKUSWB read their sources as signed and saturate to unsigned, so a negative value becomes 0, and a doubleword from 80000000h up, too large for a signed one, does as well. For uint32_t input they need a VPMINUD against 255 first.

In compiled code#

For d[i] = x > 255 ? 255 : x over uint32_t and uint8_t arrays, Clang 23 at -O2 recognizes the unsigned clamp:

• with -march=x86-64-v4 it stores each 8 results with vpmovusdb qword ptr [rdi + rdx], ymm0;
• with -march=x86-64-v3 it takes VPMINUD against 255, then VPACKUSDW and VPACKUSWB on YMM registers, with a VPERMQ after each pack to undo their lane-wise order.

GCC 14 keeps the loop scalar at -O2 for either target.

Intel’s optimization manual uses the same pair to turn the doubleword results of an AMX convolution into unsigned bytes (Section 20.11.1, Example 20-21): after the scaling in floating point and the conversion back to integers, VPMAXSD against zero applies the ReLU, which also keeps VPMOVUSDB from turning negative values into 255, and VPMOVUSDB stores 16 bytes per ZMM register. VPMOVSDB is the signed counterpart, clamping to -128 to 127.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 32):
    if k1[i]:
        xmm1.b[i] = usat(zmm2.d[i], 8)
    elif zeroing:
        xmm1.b[i] = 0
    # else: xmm1.b[i] keeps its value
for i in range(VL // 32, 16):
    xmm1.b[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 32):
    if k1[i]:
        mem.b[i] = usat(zmm2.d[i], 8)
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVUSDB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVM2B
• VPMOVM2D
• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW

All 686 AVX10.1 instructions