VPMOVUSQB

VPMOVUSQB narrows unsigned quadwords to bytes, clamping each to 255: 8 quadwords of a ZMM register become 8 bytes, 4 come from a YMM register and 2 from an XMM one, into the low bytes of an XMM register or straight to memory. The source is read as unsigned, so a negative int64_t is a large number and becomes FFh, not 0, as VPMOVUSDB’s page explains for doublewords. VPMOVQB keeps the low byte instead and covers the masked store and the zeroed upper part of the register form; VPMOVSQB clamps signed values to -128 to 127. It is part of AVX-512F.

Recorded on Zen 5#

• Unsigned limits. {evex} vpmovusqb dword ptr [mem], ymm7 turned 7Fh, 80h and 81h into 7Fh, 80h and 81h, which a signed clamp would have cut to 7Fh, and FFFFFFFFFFFFFFFFh into FFh.
• Masked store. vpmovusqb qword ptr [mem]{k6}, zmm0, with A4h in the low byte of K6, wrote bytes 2, 5 and 7: 81h, then FFh for FFh and FFh for 8000000000000000h. The other five bytes of memory kept their values.
• Zeroing. vpmovusqb xmm14{k3}{z}, ymm8, with bits 0, 1 and 3 of the four set, wrote 01h, FFh for -1 and 80h, cleared byte 2 and everything above byte 3.

In compiled code#

For d[i] = x > 255 ? 255 : x over uint64_t and uint8_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 4 results with vpmovusqb dword ptr [rax + rdx], ymm0. GCC 14 clamps with VPMINUQ against 255, then gathers and narrows the results with VPERMT2D, VPERMT2W and VPMOVWB. Both compile _mm512_mask_cvtusepi64_storeu_epi8 to the masked store vpmovusqb qword ptr [rdi]{k1}, zmm0.

AMD’s Zen 5 latency spreadsheet lists VPMOVUSQB as VPMOVQB: one macro-op on pipe FP1 or FP2 with 2, 4 and 5 cycles from XMM, YMM and ZMM sources, and two macro-ops for the memory forms.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.b[i] = usat(zmm2.q[i], 8)
    elif zeroing:
        xmm1.b[i] = 0
    # else: xmm1.b[i] keeps its value
for i in range(VL // 64, 16):
    xmm1.b[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 64):
    if k1[i]:
        mem.b[i] = usat(zmm2.q[i], 8)
    # else: mem.b[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVUSQB, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVM2Q
• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQD
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ

All 686 AVX10.1 instructions