VPMOVUSQD

VPMOVUSQD narrows unsigned quadwords to doublewords, clamping each to FFFFFFFFh: 8 quadwords of a ZMM register become 8 doublewords in a YMM register or in memory, 4 come from a YMM register and 2 from an XMM one. It is the C conversion of a uint64_t to a uint32_t with saturation. The source is unsigned, so a negative int64_t becomes FFFFFFFFh, not 0, as VPMOVUSDB’s page explains for doublewords. VPMOVQD keeps the low half instead and covers the zeroed upper part of the register form; VPMOVSQD clamps signed values. It is part of AVX-512F.

Recorded on Zen 5#

• All too large. {evex} vpmovusqd xmmword ptr [mem], ymm7 turned FFFFFFFF7FFFFFFFh, FFFFFFFFh, 100000000h and 8000000000000000h all into FFFFFFFFh: FFFFFFFFh fits, the others do not.
• Merging. vpmovusqd ymm0{k5}, zmm31, with E1h in the low byte of K5, wrote doublewords 0, 5, 6 and 7: FFFFFFFFh for FFFFFFFF80000000h and for 7FFFFFFFFFFFFFFFh, then 55h and 0. The others kept their old values, and bits 511:256 were cleared.
• Register form. {evex} vpmovusqd xmm14, xmm8 turned -1 and 7FFFFFFFh into FFFFFFFFh and 7FFFFFFFh and cleared XMM14 above bit 63.

In compiled code#

For d[i] = x > UINT32_MAX ? UINT32_MAX : x over uint64_t and uint32_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 4 results with vpmovusqd xmmword ptr [rdx + 4*rax], ymm0. GCC 14 clamps with VPMINUQ against FFFFFFFFh and picks the even doublewords of two ZMM registers with one VPERMT2D. The intrinsic is _mm512_cvtusepi64_epi32.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2 cycles from an XMM source and 4 from a YMM or ZMM one, and the memory forms two macro-ops, with 3 and 5.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        ymm1.d[i] = usat(zmm2.q[i], 32)
    elif zeroing:
        ymm1.d[i] = 0
    # else: ymm1.d[i] keeps its value
for i in range(VL // 64, 4):
    ymm1.d[i] = 0
# ymm1 is zeroed from bit 128 (xmm) or 256 (ymm) up

for i in range(VL // 64):
    if k1[i]:
        mem.d[i] = usat(zmm2.q[i], 32)
    # else: mem.d[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVUSQD, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVM2W
• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQW
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB

All 686 AVX10.1 instructions