VPMOVUSQW

VPMOVUSQW narrows unsigned quadwords to words, clamping each to 65535: 8 quadwords of a ZMM register become 8 words in an XMM register or in memory, 4 come from a YMM register and 2 from an XMM one. The source is unsigned, so a negative int64_t becomes FFFFh rather than 0, as VPMOVUSDB’s page explains. It is the saturating form of VPMOVQW, which keeps the low word, and the quadword form of VPMOVUSDW; VPMOVSQW clamps signed values. It is part of AVX-512F.

Recorded on Zen 5#

• Unsigned limits. {evex} vpmovusqw qword ptr [mem], ymm7 turned 7FFFFFFFFFFFFFFFh into FFFFh and kept 0055h, 0000h and 0001h.
• Above the signed range. vpmovusqw xmm17{k6}, zmm30, with A4h in the low byte of K6, wrote words 2, 5 and 7: 8001h stayed 8001h, where a signed clamp gives 7FFFh, and FFFFh and 8000000000000000h gave FFFFh. The other words kept XMM17’s old values, and the register was cleared from bit 128 up.
• Masked store. vpmovusqw xmmword ptr [mem]{k3}, zmm17, with EBh in the low byte of K3, wrote six words, FFFFh for 7FFFFFFFFFFFFFFFh and 8000h and 8001h unchanged among them, and left words 2 and 4 of memory as they were.

In compiled code#

For d[i] = x > 65535 ? 65535 : x over uint64_t and uint16_t arrays, Clang 23 at -O2 with -march=x86-64-v4 stores each 4 results with vpmovusqw qword ptr [rdx + 2*rax], ymm0. GCC 14 clamps with VPMINUQ against 65535 and joins the low words of four ZMM registers with VPERMT2D and VPERMT2W. Both compile _mm512_cvtusepi64_epi16 to vpmovusqw xmm0, zmm0.

AMD’s Zen 5 latency spreadsheet gives the register forms one macro-op on pipe FP1 or FP2, with 2, 4 and 5 cycles from XMM, YMM and ZMM sources, and the memory forms two macro-ops, with 3, 5 and 6.

Forms

Latency and throughput

Data flow

Where the elements of the sources go, element 0 on the right; results that depend on a control value are drawn for an example. How to read.

Operation

What the forms do, in pseudocode that our tests run against results recorded on real processors. How to read.

for i in range(VL // 64):
    if k1[i]:
        xmm1.w[i] = usat(zmm2.q[i], 16)
    elif zeroing:
        xmm1.w[i] = 0
    # else: xmm1.w[i] keeps its value
for i in range(VL // 64, 8):
    xmm1.w[i] = 0
# xmm1 is zeroed from bit 128 up

for i in range(VL // 64):
    if k1[i]:
        mem.w[i] = usat(zmm2.q[i], 16)
    # else: mem.w[i] is not written

Operands

Flags

None: XED records no flag that the forms test or change.

Exceptions

The exception class is XED's name for the set of exception conditions that a form follows. How to read.

Register forms

AVX512-E6NF

Memory forms

AVX512-E6

Attributes

What else XED records about the forms. How to read.

All forms

write masking

Memory forms

memory fault suppression

Intrinsics

The C intrinsics of Clang 23.1.2 that compile to VPMOVUSQW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.

CPUID and processors

Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.

More AVX10.1 instructions

• VPMOVQ2M
• VPMOVQB
• VPMOVQD
• VPMOVQW
• VPMOVSDB
• VPMOVSDW
• VPMOVSQB
• VPMOVSQD
• VPMOVSQW
• VPMOVSWB
• VPMOVSXBD
• VPMOVSXBQ
• VPMOVSXBW
• VPMOVSXDQ
• VPMOVSXWD
• VPMOVSXWQ
• VPMOVUSDB
• VPMOVUSDW
• VPMOVUSQB
• VPMOVUSQD
• VPMOVUSWB
• VPMOVW2M
• VPMOVWB
• VPMOVZXBD
• VPMOVZXBQ
• VPMOVZXBW
• VPMOVZXDQ
• VPMOVZXWD
• VPMOVZXWQ
• VPMULDQ
• VPMULHRSW
• VPMULHUW
• VPMULHW
• VPMULLD
• VPMULLQ
• VPMULLW
• VPMULTISHIFTQB
• VPMULUDQ
• VPOPCNTB
• VPOPCNTD

All 686 AVX10.1 instructions