Instruction
VPMOVUSQW
Narrows packed unsigned quadwords to words with unsigned saturation.
- Extensions
- Forms
- 6 (6 EVEX)
- Data
- Intel XED v2026.08.23
Forms
| Instruction | Encoding | Requires |
|---|---|---|
VPMOVUSQW xmm {k}{z}, zmm
VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512 | EVEX.512.F3.0F38.W0 14 /r | AVX10.1 or AVX512F |
VPMOVUSQW m128 {k}, zmm
VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512 | EVEX.512.F3.0F38.W0 14 /r | AVX10.1 or AVX512F |
VPMOVUSQW xmm {k}{z}, xmm
VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512 | EVEX.128.F3.0F38.W0 14 /r | AVX10.1 or AVX512F + AVX512VL |
VPMOVUSQW m32 {k}, xmm
VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512 | EVEX.128.F3.0F38.W0 14 /r | AVX10.1 or AVX512F + AVX512VL |
VPMOVUSQW xmm {k}{z}, ymm
VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512 | EVEX.256.F3.0F38.W0 14 /r | AVX10.1 or AVX512F + AVX512VL |
VPMOVUSQW m64 {k}, ymm
VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512 | EVEX.256.F3.0F38.W0 14 /r | AVX10.1 or AVX512F + AVX512VL |
Intrinsics
The C intrinsics of Clang 23.1.2 that compile to VPMOVUSQW, each with the form it compiles to and the Clang options it needs. The forms come from compiling every intrinsic and decoding the result with Intel XED; all intrinsics A–Z explains the method.
| Intrinsic | Compiles to |
|---|---|
_mm_cvtusepi64_epi16
__m128i _mm_cvtusepi64_epi16(__m128i __A) |
|
_mm_mask_cvtusepi64_epi16
__m128i _mm_mask_cvtusepi64_epi16(__m128i __O, __mmask8 __M, __m128i __A) |
|
_mm_mask_cvtusepi64_storeu_epi16
void _mm_mask_cvtusepi64_storeu_epi16(void *__P, __mmask8 __M, __m128i __A) |
|
_mm_maskz_cvtusepi64_epi16
__m128i _mm_maskz_cvtusepi64_epi16(__mmask8 __M, __m128i __A) |
|
_mm256_cvtusepi64_epi16
__m128i _mm256_cvtusepi64_epi16(__m256i __A) |
|
_mm256_mask_cvtusepi64_epi16
__m128i _mm256_mask_cvtusepi64_epi16(__m128i __O, __mmask8 __M, __m256i __A) |
|
_mm256_mask_cvtusepi64_storeu_epi16
void _mm256_mask_cvtusepi64_storeu_epi16(void *__P, __mmask8 __M, __m256i __A) |
|
_mm256_maskz_cvtusepi64_epi16
__m128i _mm256_maskz_cvtusepi64_epi16(__mmask8 __M, __m256i __A) |
|
_mm512_cvtusepi64_epi16
__m128i _mm512_cvtusepi64_epi16(__m512i __A) |
|
_mm512_mask_cvtusepi64_epi16
__m128i _mm512_mask_cvtusepi64_epi16(__m128i __O, __mmask8 __M, __m512i __A) |
|
_mm512_mask_cvtusepi64_storeu_epi16
void _mm512_mask_cvtusepi64_storeu_epi16(void *__P, __mmask8 __M, __m512i __A) |
|
_mm512_maskz_cvtusepi64_epi16
__m128i _mm512_maskz_cvtusepi64_epi16(__mmask8 __M, __m512i __A) |
|
CPUID and processors
Each form belongs to an XED ISA set. A form can be used when the processor reports every CPUID bit of one of its ISA set's alternatives.
| ISA set | CPUID | Processors in XED |
|---|---|---|
AVX512F_512 | AVX10.1 or AVX512F | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids, Knights Landing, Knights Mill |
AVX512F_128 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
AVX512F_256 | AVX10.1 or AVX512F + AVX512VL | Cannon Lake, Ice Lake (client), Tiger Lake, Nova Lake, Skylake-SP, Cascade Lake, Cooper Lake, Ice Lake (server), Sapphire Rapids, Emerald Rapids, Granite Rapids, Diamond Rapids |
More AVX10.1 instructions
- VPMOVQ2M
- VPMOVQB
- VPMOVQD
- VPMOVQW
- VPMOVSDB
- VPMOVSDW
- VPMOVSQB
- VPMOVSQD
- VPMOVSQW
- VPMOVSWB
- VPMOVSXBD
- VPMOVSXBQ
- VPMOVSXBW
- VPMOVSXDQ
- VPMOVSXWD
- VPMOVSXWQ
- VPMOVUSDB
- VPMOVUSDW
- VPMOVUSQB
- VPMOVUSQD
- VPMOVUSWB
- VPMOVW2M
- VPMOVWB
- VPMOVZXBD
- VPMOVZXBQ
- VPMOVZXBW
- VPMOVZXDQ
- VPMOVZXWD
- VPMOVZXWQ
- VPMULDQ
- VPMULHRSW
- VPMULHUW
- VPMULHW
- VPMULLD
- VPMULLQ
- VPMULLW
- VPMULTISHIFTQB
- VPMULUDQ
- VPOPCNTB
- VPOPCNTD
Sources
- Intel XED v2026.08.23 (commit
0bcb6237345c): forms, encodings, ISA sets, CPUID bits and chip model. - Clang's x86 intrinsic headers, LLVM 23.1.2 (commit
85ac56026243): the intrinsics, their signatures and doc comments, and the Clang of that release, which compiled each of them. - Intel Advanced Vector Extensions 10.2 Architecture Specification, revision 6.0 (361050-006, January 2026)
The tables are derived from Intel XED, Copyright Intel Corporation, licensed under the Apache License 2.0; x86-64.net converted and reformatted them. The intrinsics and their signatures come from Clang, part of the LLVM Project, licensed under the Apache License 2.0 with LLVM Exceptions. The text is our own.